nsc800 National Semiconductor Corporation, nsc800 Datasheet - Page 9

• Manufacturer Part Number: nsc800
• Description: Nsc800tm High-performance Low-power Cmos Microprocessor
• Manufacturer: National Semiconductor Corporation

6 0 Pin Descriptions
Status (SO S1) Bus status outputs provide encoded infor-
mation regarding the current M cycle as follows
rupt (RSTA RSTB RSTC INTR NMI)
Note 1 During halt CPU continues to do dummy opcode fetch from location
following the halt instruction with a halt status This is so CPU can continue
to do its dynamic RAM refresh
Note 2 No early status is provided for interrupt or hardware restarts
7 0 Connection Diagrams
ALE is not suppressed in this cycle
Opcode Fetch
Memory Read
Memory Write
I O Read
I O Write
Halt
Internal Operation
Acknowledge of Int
This is the cycle that occurs immediately after the CPU accepts an inter-
Machine Cycle
See NS Package D40C or N40A
Order Number NSC800D or N
Dual-In-Line Package
Top View
S0
1
0
1
0
1
0
0
1
Status
S1
1
1
0
1
0
0
1
1
(Continued)
IO M
TL C 5171– 10
0
0
0
1
1
0
0
0
RD
0
0
1
0
1
0
1
1
Control
WR
1
1
0
1
0
1
1
1
9
6 3 INPUT OUTPUT SIGNALS
Multiplexed Address Data AD(0– 7) Active high
At RD Time
At WR Time
At Falling Edge Least significant byte of address
of ALE Time
During BREQ
BACK Cycle
See NS Package E44B or V44A
Order Number NSC800E or V
Chip Carrier Package
Input data to CPU
Output data from CPU
during memory reference cycle 8-bit
port address during I O reference
cycle
High impedance
Top View
TL C 5171– 11