nsc800 National Semiconductor Corporation, nsc800 Datasheet - Page 24

• Manufacturer Part Number: nsc800
• Description: Nsc800tm High-performance Low-power Cmos Microprocessor
• Manufacturer: National Semiconductor Corporation

Figure 19 depicts the status of the flip flops during a sample
9 0 Timing and Control
so that the complete state of the CPU just prior to the non-
maskable interrupt may be restored The method of restor-
ing the status of IFF
Non-Maskable Interrupt (RETN) instruction Since this in-
struction indicates that the non-maskable interrupt service
routine is completed the contents of IFF
back into IFF
acceptance of the non-maskable interrupt will be automati-
cally restored
series of interrupt instructions
Interrupt Control Register The interrupt control register
(ICR) is a 4-bit write only register that provides the program-
mer with a second level of maskable control over the four
maskable interrupt inputs
The ICR is internal to the NSC800 CPU but is addressed
through the I O space at I O address port X’BB Each bit in
the register controls a mask bit dedicated to each maskable
interrupt RSTA RSTB RSTC and INTR For an interrupt
request to be accepted on any of these inputs the corre-
sponding mask bit in the ICR must be set (
and IFF
control over individual interrupt inputs rather than just a sys-
tem wide enable or disable
For example In order to enable RSTB CPU interrupts must
be enabled and IEB must be set
At reset IEI bit is set and other mask bits IEA IEB IEC are
cleared This maintains the software compatibility between
NSC800 and Z80A
Execution of an I O block move instruction will not affect
the state of the interrupt control bits The only two instruc-
tions that will modify this write only register are OUT (C) r
and OUT (N) A
Bit
0
1
2
3
2
must be set This provides the programmer with
1
Name
so that the status of IFF
IEC
IEB
IEA
IEI
1
is through the execution of a Return
Interrupt Enable for INTR
Interrupt Enable for RSTC
Interrupt Enable for RSTB
Interrupt Enable for RSTA
Function
(Continued)
1
2
just prior to the
are now copied
e
1) and IFF
TL C 5171–26
1
24
FIGURE 19 IFF
Operation
Initialize
RETN
RETN
INTR
INTR
RET
RET
NMI
NMI
EI
EI
EI
Operation has been Completed
IFF
1
0
1
0
1
1
0
1
0
0
0
1
1
and IFF
1
IFF
0
1
0
1
1
1
1
0
0
0
1
1
2
2
States Immediately after the
Interrupt Disabled
Interrupt Enabled after
next instruction
Interrupt Disable and INTR
Being Serviced
Interrupt Enabled after
next instruction
Interrupt Enabled
Interrupt Disabled
Interrupt Enabled
Interrupt Disabled
Interrupt Disabled and NMI
Being Serviced
Interrupt Disabled and INTR
Being Serviced
Interrupt Enabled after
next instruction
Interrupt Enabled
Comment