nsc800 National Semiconductor Corporation, nsc800 Datasheet - Page 36

• Manufacturer Part Number: nsc800
• Description: Nsc800tm High-performance Low-power Cmos Microprocessor
• Manufacturer: National Semiconductor Corporation

12 6 8-Bit Arithmetic
REGISTER ADDRESSING ARITHMETIC
ADD
Add contents of register r to the
Accumulator
A
Timing
Addressing Mode
ADC
Add contents of register r plus the carry flag to the Accu-
mulator
A
7
1
Op
ADD
ADC
INC
SUB
SBC
DEC
NEG
6
0
A
A
Before
5
0
a
DAA
A r
A r
a
C
0
0
0
0
0
0
1
1
1
0
0
1
1
r
4
0
r
a
3
0
(Bits 7-4)
CY
Upper
Value
Digit
Hex
A-F
A-F
0-9
0-8
0-9
9-F
0-2
0-2
0-3
0-9
0-8
7-F
6-F
In
2
P V Set according to overflow
P V Set if result exceeds 2’s com-
1
r
H Set if carry from bit 3
N Reset
C Set if carry from bit 7
H Set if carry from bit 3
N Reset
C Set if carry from bit 7
S Set if negative result
Z Set if zero result
S Set if negative result
Z Set if zero result
Before
0
DAA
condition
M cycles 1
T states 4
Source Register
Destination Implied
plement range
H
0
0
1
0
0
1
0
0
1
0
1
0
1
(Bits 3-0)
Lower
Value
Digit
Hex
A-F
A-F
A-F
0-9
0-3
0-9
0-3
0-9
0-3
0-9
6-F
0-9
6-F
In
Number
Added
Byte
To
FA
00
06
06
60
66
66
60
66
66
00
A0
9A
After
DAA
C
0
0
0
1
1
1
1
1
1
0
0
1
1
36
Timing
Addressing Mode
SUB
Subtract the contents of register r from the Accumulator
A
Timing
Addressing Mode
SBC
Subtract contents of register r and the carry bit C from the
Accumulator
A
Timing
Addressing Mode
AND
Logically AND the contents of the r register and the Accu-
mulator
A
7
1
7
1
7
1
6
0
6
0
6
0
A
A
A
5
0
5
0
5
0
r
A r
r
b
b
4
4
0
4
1
1
r
r
r
b
3
1
3
0
3
1
CY
2
2
2
P V Set if result exceeds 8-bit 2’s
P V Set if result exceeds 8-bit 2’s
P V Set if result parity is even
1
1
1
r
r
r
N Set
N Set
N Reset
S Set if result is negative
H Set if borrow from bit 4
C Set according to borrow
S Set if result is negative
H Set if borrow from bit 4
C Set according to borrow
S Set if result is negative
H Set
C Reset
Z Set if result is zero
Z Set if result is zero
Z Set if result is zero
0
0
0
M cycles 1
T states 4
Source Register
Destination Implied
complement range
M cycles 1
T states 4
Source Register
Destination Implied
complement range
M cycles 1
T states 4
Source Register
Destination Implied