nsc800 National Semiconductor Corporation, nsc800 Datasheet - Page 16

• Manufacturer Part Number: nsc800
• Description: Nsc800tm High-performance Low-power Cmos Microprocessor
• Manufacturer: National Semiconductor Corporation

9 0 Timing and Control
9 2 CPU TIMING
The NSC800 uses a multiplexed bus for data and address-
es The 16-bit address bus is divided into a high-order 8-bit
address bus that handles bits 8–15 of the address and a
low-order 8-bit multiplexed address data bus that handles
bits 0 –7 of the address and bits 0–7 of the data Strobe
outputs from the NSC800 (ALE RD and WR) indicate when
a valid address or data is present on the bus IO M indi-
cates whether the ensuing cycle accesses memory or I O
FIGURE 9a Opcode Fetch Cycles without WAIT States
FIGURE 9b Opcode Fetch Cycles with WAIT States
(Continued)
16
Figure 9 illustrates the timing relationship for opcode fetch
During an input or output instruction the CPU duplicates the
lower half of the address AD(0– 7) onto the upper address
bus A(8 – 15) The eight bits of address will stay on A(8–
15) for the entire machine cycle and can be used for chip
selection directly
cycles with and without a wait state
TL C 5171 – 15
TL C 5171 – 16