nsc800 National Semiconductor Corporation, nsc800 Datasheet - Page 17

• Manufacturer Part Number: nsc800
• Description: Nsc800tm High-performance Low-power Cmos Microprocessor
• Manufacturer: National Semiconductor Corporation

9 0 Timing and Control
During the opcode fetch the CPU places the contents of
the PC on the address bus The falling edge of ALE indi-
cates a valid address on the AD(0–7) lines The WAIT input
is sampled during t
insert a wait state (t
2
w
) WAIT is sampled again during t
and if active causes the NSC800 to
FIGURE 10a Memory Read Write Cycles without WAIT States
FIGURE 10b Memory Read and Write with WAIT States
(Continued)
w
so
17
that when it goes inactive the CPU continues its opcode
fetch by latching in the data on the rising edge of RD from
the AD(0– 7) lines During t
7) has the dynamic RAM refresh address from register R
and A(8– 15) the interrupt vector from register I
3
RFSH goes active and AD(0–
TL C 5171 – 17
TL C 5171 – 18