nsc800 National Semiconductor Corporation, nsc800 Datasheet - Page 42

• Manufacturer Part Number: nsc800
• Description: Nsc800tm High-performance Low-power Cmos Microprocessor
• Manufacturer: National Semiconductor Corporation

12 6 8-Bit Arithmetic
XOR
The data in memory location m
the data in the Accumulator
A
Timing
Addressing Mode
Timing
Addressing Mode
CP
Compare the data in memory location m
the Accumulator via subtraction
A
Timing
Addressing Mode
7
1
7 6
1 1 N
1 0
7
1
7 6
1 1 N
1 0
b
6
0
6
0
m
1
A
m
5
1
5
1
5
1
5
1
m
1
X
X
Z
1
4
0
4
1
m
4 3 2 1 0
1 1 1 0 1
0 1 1 1 0
4 3 2 1 0
1 1 1 0 1
1 1 1 1 0
d
d
1
3
1
3
1
2
1
2
1
P V Set if result parity is even
P V Set if result exceeds 8-bit 2’s
1
1
1
1
H Reset
N Reset
C Reset
H Set if borrow from bit 4
N Set
C Set according to borrow
S Set if result is negative
Z Set if result is zero
S Set if result is negative
Z Set if result is zero
0
0
0
0
M cycles 2
T states 7 (4 3)
Source Register Indexed
Destination Implied
M cycles 5
T states 19 (4 4 3 5 3)
Source Indexed
Destination Implied
complement range
condition
M cycles 2
T states 7 (4 3)
Source Register Indirect
Destination Implied
1
XOR (HL)
XOR (IX
CP (HL)
CP (IX
XOR (IY
CP (IY
is exclusively OR’ed with
(Continued)
a
a
1
a
a
d) (for N
d) (for N
with the data in
d) (for N
d) (for N
X
X
e
e
X
X
e
e
0)
1)
0)
1)
42
Timing
Addressing Mode
INC
Increment data in memory location m
m
Timing
Addressing Mode
Timing
Addressing Mode
DEC
Decrement data in memory location m
m
7
0
7 6
1 1 N
0 0
1
1
6
0
m
5
1
m
m
5
1
m
X
1
1
1
1
4
1
a
b
4 3 2 1 0
1 1 1 0 1
1 0 1 0 0
d
1
1
3
0
2
1
P V Set if data was X’7F before op-
P V Set only if m
1
0
N Reset
N Set
S Set if result is negative
H Set according to carry from bit
C N A
S Set if result is negative
H Set according to borrow from
C N A
Z Set if result is zero
Z Set if result is zero
0
0
M cycles 5
T states 19 (4 4 3 5 3)
Source Indexed
Destination Implied
3
eration
M cycles 3
T states 11 (4 4 3)
Source Register Indexed
Destination Register Indexed
M cycles 6
T states 23 (4 4 3 5 4 3)
Source Indexed
Destination Indexed
bit 4
operation
INC (HL)
INC (IX
INC (IY
1
1
a
a
1
was X’80 before
d) (for N
d) (for N
X
X
e
e
0)
1)