MT8930CE Zarlink Semiconductor, MT8930CE Datasheet - Page 5

• Manufacturer Part Number: MT8930CE
• Description: Description = 4 Wire Full-duplex 2B+D (192Kb/s) Data Format Isdn S And T Subscriber Network Interface Circuit With Controllerless Mode ;; Package Type = Pdip ;; No. Of Pins = 28
• Manufacturer: Zarlink Semiconductor

Data Sheet
Functional Description
The MT8930C Subscriber Network Interface Circuit
(SNIC) is a multifunction transceiver providing a
complete interface to the S/T Reference Point as
specified in ETS 300-012, CCITT Recommendation
I.430
point-to-point
transmission, the SNIC may be used at either end of
the digital subscriber loop. A programmable digital
interface allows the MT8930C to be configured as a
Network
Equipment (TE) device.
The SNIC supports 192 kbit/s (2B+D + overhead) full
duplex data transmission on a 4-wire balanced
transmission line. Transmission capability for both B
and D channels, as well as related timing and
synchronization functions, are provided on chip. The
signalling capability and procedures necessary to
enable customer terminals (TEs) to be activated and
deactivated,
functionality. The SNIC handles D-channel resource
allocation and prioritization for access contention
resolution and signalling requirements in passive bus
line configurations. Control and status information
and
Termination
IRQ, NDA
R/W/WR
AS/ALE
ANSI
Cmode
Cmode
DS/RD
form
HALF
DSTo
HALF
DSTo
and
P/SC
F0od
F0od
DSTi
DSTi
DinB
C4bi
VSS
C4bi
VSS
F0bi
F0bi
AFT
CS
NT
NT
IC
IC
T1.605.
point-to-multipoint
part
10
11
12
13
14
10
11
12
13
14
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
(NT)
NT MODE
NT MODE
Figure 3 - SNIC Pin Connections in Various Modes
of
or
Implementing
28
27
26
25
24
23
22
21
20
19
18
17
16
28
27
26
25
24
23
22
21
20
19
18
17
16
15
15
the
as
VDD
VBias
LTx
LRx
STAR
Rsti
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VDD
VBias
LTx
LRx
STAR
Rsti
DR
AR
M/Si
MCHo
MFRi
SYNC/BA
IS1
IS0
a
MT8930C’s
voice/data
CONTROLLERLESS MODE
Terminal
CONTROLLER MODE
both
allows implementation of maintenance functions and
monitoring of the device and the subscriber loop.
An HDLC transceiver is included on the SNIC for link
access
Depacketized data is passed to and from the
transceiver via the microprocessor port. Two 19 byte
deep FIFOs, one for transmit and one for receive,
are provided to buffer the data. The HDLC block can
be set up to transmit or receive to/from either the
S-interface port or the ST-BUS port. Further, the
transmit destination and receive source can be
independently selected, e.g., transmit to S-interface
while receiving from ST-BUS.
receive paths can be separately enabled or disabled.
Both, one and two byte address recognition is
supported by the SNIC. A transparent mode allows
data to be passed directly to the D channel without
being packetized.
A block diagram of the MT8930C is shown in Figure
1.
CCITT compatible S/T interface
interface), a 2048 kbit/s ST-BUS serial port, and a
general purpose parallel microprocessor port. This
8-bit parallel port is compatible with both Motorola or
IRQ, NDA
R/W/WR
AS/ALE
The SNIC has three interface ports: a 4-wire
Cmode
Cmode
DS/RD
DCack
HALF
DSTo
HALF
DSTo
DReq
C4bo
C4bo
P/SC
F0bo
F0od
F0bo
F0od
DSTi
DSTi
DinB
VSS
VSS
PRI
CK
CS
CK
protocol
10
11
12
13
14
10
11
12
13
14
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
TE MODE
TE MODE
handling
28
27
26
25
24
23
22
21
20
19
18
17
16
28
27
26
25
24
23
22
21
20
19
18
17
16
15
15
VDD
VBias
LTx
LRx
Rsto
Rsti
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VDD
VBias
LTx
LRx
Rsto
Rsti
DR
AR
M/So
MCHi
MFRo
SYNC/BA
IS1
IS0
via
The transmit and
MT8930C
(subscriber loop
the
D-channel.
5