MT8930CE Zarlink Semiconductor, MT8930CE Datasheet - Page 10

• Manufacturer Part Number: MT8930CE
• Description: Description = 4 Wire Full-duplex 2B+D (192Kb/s) Data Format Isdn S And T Subscriber Network Interface Circuit With Controllerless Mode ;; Package Type = Pdip ;; No. Of Pins = 28
• Manufacturer: Zarlink Semiconductor

Line Wiring Configuration
The MT8930C can interface to any of the three
wiring configurations which are specified by CCITT
Recommendation I.430 and ANSI T1.605 (refer to
Figs. 8 to 10). These consist of a point-to-point or
one of the two point-to-multipoint configurations (i.e.,
short passive bus or the extended passive bus). The
selection of line configurations is performed using
the timing bit (B4 of NT Mode Control Register).
For the short passive bus, TE devices are connected
at random points along the cable. However, for the
extended passive bus all connection points are
grouped at the far end of the cable from the NT.
MT8930C
10
Info0
Info2
Info4
TE State Activation Diagram
NT State Activation Diagram
Signals from NT to TE
No Signal
Valid frame structure with
all B, D, D-echo and A bits
set to ‘0’
Valid frame with data in B,
D, D-echo channels. Bit A is
set to 1.
Deactivated
send Info0
Activation
send Info2
Pending
Figure 7 - Link Activation Protocol, State Diagram
DR = 1
DR = 1
Sync = 1
AR = 1
BA = 1
BA = 0
Sync = 0
AR = 1
Info0
Info1
Info3
No Signal
Continuous Signal of +‘0’, -‘0’
and six ‘1’s
Valid frame with data in B & D
Bits
Activation Request
Signals from TE to NT
send Info1 if BA = 0
send Info0 if BA = 1
Deactivated
send Info3
Activated
send Info4
send Info0
Activated
Sync = 1
BA = 0
DR = 1
AR = 1
DR = 1
(1)
For an NT SNIC in fixed timing mode, the VCO and
Rx filters/peak detectors are disabled and the
threshold voltage is fixed. However, for a TE SNIC
or an NT SNIC (in adaptive timing mode), the VCO
and Rx filters/peak detectors are enabled. In this
manner, the device can compensate for variable
round trip delays and line attenuation using a
threshold voltage set to a fixed percentage of the
pulse peak amplitude.
Another operation can be implemented using the
SNIC in the star configuration as shown in Figure 14.
This mode allows multiple NTs, with physically
independent S-Busses, to share a common input
source and transfer information down the S-Bus to
Sync = 1
A = 1 &
BA =0
Sync = 0
Time out
DR = 1
Sync = 1
Where: BA
Note 1: signal is not timebase locked to NT.
Note 2: Sync/BA bit of the Status Register
send Info3 if Sync = 1
send Info0 if Sync = 0
Deactivation
Send Info0
A = 0
Pending
Synchronized
DR = Deactivation Request
AR = Activation Request
Sync
A = Activation bit
Time out = 32 ms Timer Signal
is configured as Sync bit when
AR = 1 and DR = 0, or as BA bit
when AR = 0 or DR = 1. A change in
the state of the AR and/or DR bits
will cause a change in the function
of the Sync/BA bit in the following
ST-BUS frame.
(2)
(2)
= Bus Activity
= Frame Sync Signal
Data Sheet