MT8930CE Zarlink Semiconductor, MT8930CE Datasheet - Page 14

• Manufacturer Part Number: MT8930CE
• Description: Description = 4 Wire Full-duplex 2B+D (192Kb/s) Data Format Isdn S And T Subscriber Network Interface Circuit With Controllerless Mode ;; Package Type = Pdip ;; No. Of Pins = 28
• Manufacturer: Zarlink Semiconductor

Some registers are classified as asynchronous and
others as synchronous. Synchronous registers are
single-buffered and require synchronous access.
Not all the synchronous registers have the same
access times, but all can be accessed synchronously
in the time during which the NDA signal is low
(refer to Fig. 5). Therefore, it is recommended that
the user make use of the NDA signal to access these
registers.
common circuitry, it is essential that the register be
read before being written.
important as a write cycle will overwrite the last data
received. These parallel accesses must be refreshed
every frame. Asynchronous registers, on the other
hand, can be accessed at any time.
When the Cmode pin is low, controllerless mode is
selected and the parallel port reverts to hardwired
control/status pins.
function
microprocessor.
parallel bus has direct connection to the relevant
control/status registers (refer to Pin Description).
Discrete
the respective pins.
(P/SC determines whether the microport pins or
the C-channel bits on DSTi stream are the control
source of the device.
to be the source, P/SC
microport pins are ignored and the C-channel is
loaded into the C-channel Control Register.
MT8930C
14
A
S
Y
N
C
S
Y
N
C
A4
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
Address Lines
without
logic
A3
Since the synchronous registers use
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
can
In the controllerless mode, the
the
This allows the MT8930C to
A1
0
0
1
1
0
0
1
1
0
0
0
1
0
0
1
1
0
0
1
1
If the C-channel is selected
be used to drive/sense
need
In this mode, pin 11
is
A0
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
This sequence is
for
tied low, then the
HDLC Address Byte #1 Register
HDLC Address Byte #2 Register
HDLC Interrupt Mask Register
a
C-channel Control Register
Table 2. SNIC Address Map
ST-BUS Control Register
HDLC Control Register 1
HDLC Control Register 2
Master Control Register
controlling
S-Bus Tx B1-channel
S-Bus Tx B2-channel
S-Bus Tx D-channel
Control Register 1
DSTo B1-channel
DSTo B2-channel
DSTo C-channel
DSTo D-channel
HDLC Tx FIFO
Not Available
Write
The data in TE or NT Mode Status Register,
depending upon the mode selected, is always sent
out on the C-channel of DSTo.
microprocessor control mode the user can overwrite
this data by writing to the DSTo C-channel Register.
This access can be done anytime outside the frame
pulse interval of the ST-BUS frame. Data written in
the current ST-BUS frame will only appear in the C-
channel of the following frame.
The least significant bit (B0) of the C-channel
Register, selects between the control register or the
diagnostic register. Setting the B0 of the C-channel
Register to ’0’ allow access to the control register.
Setting the LSB of the C-channel Register to ’1’ allow
access to the diagnostic register. The interpretation
of each register is defined in Tables 13 and 14 for NT
mode or Tables 16 and 17 for the TE mode.
It is important to note that in TE mode, the C-channel
Diagnostic Register should be cleared while the
device is not in the active state (IS0, IS1
is accomplished by setting the ClrDia bit of the C-
channel Control Register to 1 until the device is
activated. In serial control mode, the C-channel on
the ST-BUS is loaded into the C-channel Control
Register in every ST-BUS frame; the user should
make sure that a 1 is written to the ClrDia bit in every
frame. However, in parallel control mode the user
needs to set the ClrDia bit only once to keep the
HDLC Interrupt Status Register
C-channel Status Register
Master Status Register
HDLC Status Register
S-Bus Rx B1-channel
S-Bus Rx B2-channel
S-Bus Rx D-channel
DSTi B1-channel
DSTi B2-channel
DSTi C-channel
DSTi D-channel
HDLC Rx FIFO
Not available
Read
verify
verify
verify
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Data Sheet
However, in
≠
1,1). This