MT8930CE Zarlink Semiconductor, MT8930CE Datasheet - Page 2

• Manufacturer Part Number: MT8930CE
• Description: Description = 4 Wire Full-duplex 2B+D (192Kb/s) Data Format Isdn S And T Subscriber Network Interface Circuit With Controllerless Mode ;; Package Type = Pdip ;; No. Of Pins = 28
• Manufacturer: Zarlink Semiconductor

MT8930C
2
Pin Description
DIP
1
2
3
4
5
6
7
8
R/W/WR, AFT/PRI
Pin #
IRQ/NDA, DCack
PLCC
AS/ALE, P/SC
DS/RD, DinB
13
14
2
3
4
7
8
9
CS, DReq
Cmode
CK/NT
HALF
DSTo
F0od
DSTi
VSS
C4b
F0b
Cmode
CK/NT
Name
HALF
DSTo
F0od
DSTi
C4b
F0b
10
11
12
13
14
1
2
3
4
5
6
7
8
9
28 PIN PDIP
HALF Input/Output: this is an input in NT mode and an output in TE mode identifying
which half of the S-interface frame is currently being written/read over the ST-BUS
(HALF = 0 sampled on the falling edge of C4b within the frame pulse low window,
identifies the information to be transmitted/received in the first half of the S-Bus frame
while HALF = 1 identifies the information to be transmitted/received into the second half
of the S-Bus frame). Tying this pin to V
free run. This signal can also be accessed from the ST-BUS C-channel.
4.096 MHz Clock: a 4.096 MHz ST-BUS Data Clock input in NT mode.
In TE mode, a 4.096 MHz output clock phase-locked to the line data signal.
Frame Pulse: an active low frame pulse input indicating the beginning of active ST-
BUS channel times in NT mode. Frame pulse output in TE mode.
Delayed Frame Pulse Output: an active low delayed frame pulse output indicating
the end of active ST-BUS channels for this device.
to other ST-BUS devices to share an ST-BUS stream.
Data ST-BUS Input: a 2048 kbit/s serial PCM/data ST-BUS input with D, C, B1, and B2
channels assigned to the first four timeslots. These channels contain data to be
transmitted on the line and chip control information.
Data ST-BUS Output: a 2048 kbit/s serial PCM/data ST-BUS output with D, C, B1 and
B2 channels assigned to the first four timeslots respectively. The remaining timeslots
are placed into high impedance. These channels contain data received from the line
and chip status information.
Controller Mode Select Input: when high, microprocessor control is selected. When
low the controllerless mode is enabled and the microport pins are redefined as control
inputs and status outputs.
TE Clock/Network Termination Mode Select Input. For TE mode, this pin must be
tied to V
applications). For NT mode, this pin must be tied to V
section for further explanation. A pull-up resistor is needed when driven by a TTL
device.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SS
or to a 4.096 MHz clock (a clock is required for standard ISDN TE
VDD
VBias
LTx
LRx
STAR/Rsto
Rsti
AD7, DR
AD6, AR
AD5, M/S
AD4, MCH
AD3, MFR
AD2, SYNC/BA
AD1, IS1
AD0, IS0
Figure 2 - Pin Connections
R/W/WR, AFT/PRI
DS/RD, DinB
Cmode
CK/NT
DSTo
Description
F0od
DSTi
NC
NC
NC
NC
SS
or V
18 19 20 21 22
7
8
9
10
11
12
13
14
15
16
17
6 5 4 3 2
DD
in NT mode will allow the device to
DD
44 PIN PLCC
. Refer to “ST-BUS Interface”
23
Can be used to daisy chain
1
24 25 26 27 28
44 43 42 41 40
29
39
38
37
36
35
34
33
32
31
30
Data Sheet
NC
STAR/Rsto
Rsti
NC
AD7, DR
AD6, AR
NC
AD5, M/S
AD4, MCH
AD3, MFR
NC