MT8930CE Zarlink Semiconductor, MT8930CE Datasheet - Page 22

• Manufacturer Part Number: MT8930CE
• Description: Description = 4 Wire Full-duplex 2B+D (192Kb/s) Data Format Isdn S And T Subscriber Network Interface Circuit With Controllerless Mode ;; Package Type = Pdip ;; No. Of Pins = 28
• Manufacturer: Zarlink Semiconductor

MT8930C
Note 1:
Note 2:
22
B7-B2 R1A7-R1A2 A six bit mask used to interrogate the first byte of the received address (where B7 is MSB).
B7-B1 R2A7-R2A1 A seven bit mask used to interrogate the second byte of the received address (where B7 is
BIT
BIT
BIT
B1
B0
B0
B7
B6
B5
B4
B3
B2
B1
B0
The C-channel Control Register is updated once every ST-BUS frame. Therefore, this register should not be written to
Allow one ST-BUS frame to input the C-channel and one ST-BUS frame to establish the connection.
more than once per frame, otherwise, the last access will override previous ones.
TxMFR
RegSel
Table 13. NT Mode C-channel Control Register
NAME
NAME
NAME
Timing
HALF
A1En
A2En
DinB
M/S
AR
DR
NA
Table 11. HDLC Address Recognition Register 1 (Read/Write Add. 00110
Table 12. HDLC Address Recognition Register 2 (Read/Write Add. 00111
MSB). If address recognition is enabled, any packet failing the address comparison will
not be stored in the Rx FIFO. This mask is ignored if the address is a Broadcast (i.e., R2A
= 1111111).
If ’0’, the second byte of the address field will not be used during address recognition.
If ’1’ and the address recognition is enabled, the seven most significant bits of the second
address byte will be compared with the first seven bits of this register.
Setting this bit will initiate the activation of the S-Bus.
If ’0’, the device will remain in the present state.
Setting this bit will initiate the deactivation of the S-Bus.
If ’0’, the device will remain in the present state. This bit has priority over AR.
If ’1’, the D-channel will be placed in the B1 timeslot allocating 64 kbit/s to the D-channel.
A ’0’ will set the NT in a short passive bus configuration using a fixed timing source (no
compensation for line length).
A ’1’ will set the NT in a point-to-point or extended passive bus configuration with adaptive
timing compensation.
This bit represents the state of the transmitted M/S-bit. M when HALF=0 and S when
HALF=1.
The state of this bit identifies which half of the frame will be transmitted on the S-
Bus. The operation of this signal is similar to that of the HALF pin.
A ’1’ in this bit, while HALF = 0, will force the transmission of a multiframe sequence in the
Fa and N bits, i.e., Fa=1 and N=0. A ‘0’ will resume normal operation, i.e., Fa=0 and N=1.
If the register select bit is set to ’1’, the control register is redefined as the diagnostic
register. A ’0’ give access to the control register.
If address recognition is enabled, any packet failing the address comparison will not be
stored in the Rx FIFO.
Not applicable to address recognition.
If ’0’, the first byte of the address field will not be used during address recognition.
If ’1’ and the address recognition is enabled, the six most significant bits of the first
address byte will be compared with the first six bits of this register.
If ’0’, the D-channel will assume its position with a 16 kbit/s bandwidth.
DESCRIPTION
DESCRIPTION
DESCRIPTION
(2)
(Write Add. 01000
B
and B0 = 0)
(1)
B
B
)
)
Data Sheet
(1)