MT8930CE Zarlink Semiconductor, MT8930CE Datasheet - Page 12

• Manufacturer Part Number: MT8930CE
• Description: Description = 4 Wire Full-duplex 2B+D (192Kb/s) Data Format Isdn S And T Subscriber Network Interface Circuit With Controllerless Mode ;; Package Type = Pdip ;; No. Of Pins = 28
• Manufacturer: Zarlink Semiconductor

ST-BUS Interface
The ST-BUS is a synchronous time division
multiplexed serial bussing scheme with data streams
operating at 2048 kbit/s configured as 32, 64 kbit/s
channels (refer to Fig. 11). Synchronization of the
data transfer is provided from a frame pulse which
identifies the frame boundaries and repeats at an 8
kHz rate.
(F0b) defines the ST-BUS frame boundaries. All
data is clocked into the device on the rising edge of
the 4096 kHz clock (C4b) three quarters of the way
into the bit cell, while data is clocked out on the
falling edge of the 4096 kHz clock at the start of the
bit cell.
All timing signals (i.e. F0b & C4b) are identified as
bidirectional (denoted by the terminating b). The
I/O configuration of these pins is controlled by the
mode of operation (NT or TE). In the NT mode, all
synchronized signals are supplied from an external
source and the SNIC uses this timing while
transferring information to and from the S or
ST-BUS.
phase-locked loop extracts timing from the received
data on the S-Bus and
4096 kHz (C4b) and frame pulse (F0b).
analog phase-locked loop also maintains proper
phase relation between the timing signals as well as
filtering out jitter which may be present on the
received line port.
MT8930C
12
F0b
C4b
ST-BUS
BIT CELLS
In the TE mode,
Channel
Figure 4 shows how the frame pulse
0
Channel 31
Bit 0
Figure 12 - Clock & Frame Alignment for ST-BUS Streams
Channel
1
generates
an on-board analog
Bit 7
Channel 0
Channel
Figure 11 - ST-BUS Stream Format
Bit 7
2
the
Bit 6
125 µs
system
Bit 5
The
• • •
Channel 0
Bit 4
Bit 6
When the TE mode is selected by tying the CK/NT
pin low, a continuous INFO0 signal on the receiver
will cause the PLL frequency to drift from its nominal
4.096 MHz value (C4b output). Hence, transmitted
INFO1 from the TE will not be at 192 kbps as
required in I.430 and T1.605. However, if the user’s
application requires the transmission of INFO1 at
exactly 192 kbit/s or the presence of an exact 4.096
MHz C4b clock at all times, then a 4.096 MHz clock
should be connected to the CK/NT pin.
This input clock serves to configure the device in TE
mode and to train the PLL in the absence of an
INFO2 or INFO4 signal on the line.
The SNIC uses the first four channels on the
ST-BUS (as shown in Figure 4).
distribution of
provides a delayed frame pulse (F0od) to eliminate
the need for a channel
signal is used to drive subsequent devices in the
daisy chain (refer Figure 13).
arrangement, only the first SNIC in the chain will
receive the system frame pulse (F0b) with the
following devices receiving its predecessor’s delayed
output frame pulse (F0od).
The SNIC makes efficient use of its TDM bus
through the Star configuration. It does so by sharing
four common ST-BUS channels to multiple NT
devices.
(8/2048) ms
Bit 3
Channel
Bit 2
Channel 0
30
Bit 5
the
Bit 1
Channel
serial
31
assignment circuit. This
Bit 0
stream,
Channel 0
Channel
Bit 4
0
In this type of
To simplify the
Data Sheet
the
SNIC