MT8930CE Zarlink Semiconductor, MT8930CE Datasheet - Page 16

• Manufacturer Part Number: MT8930CE
• Description: Description = 4 Wire Full-duplex 2B+D (192Kb/s) Data Format Isdn S And T Subscriber Network Interface Circuit With Controllerless Mode ;; Package Type = Pdip ;; No. Of Pins = 28
• Manufacturer: Zarlink Semiconductor

Interframe Time Fill
When the HDLC Tranceiver is not sending packets,
the transmitter can be in one of two states mentioned
below depending on the status of the IFTF bit in the
HDLC Control Register 1.
i) Idle State
The Idle state is defined as 15 or more contiguous
ONEs. When the HDLC Protocoller is observing this
condition on the receiving channel, the Idle bit in the
HDLC Status Register is set HIGH. On the transmit
side, the Protocoller ends the transmission of all
ones (idle state) when data is loaded into the
transmit FIFO.
CCITT I.430 Specification requires every TE that
does not have layer 2 frames to transmit, to send
binary ONEs on the D-channel. In this manner, other
TEs on the line will have the opportunity to access
the D-channel using the priority mechanism circuitry.
ii) Flag Fill State
The HDLC Protocoller transmits continuous flags
(7E
state when data is loaded into the transmit FIFO.
The reception of the interframe time fill will have the
effect of setting the idle bit in the HDLC Status
Register is set to ’0’.
HDLC Transmitter
On power up, the HDLC transmitter is disabled and
in the idle state.
setting the TxEN bit in the HDLC Control Register 1.
To start a packet, the data is written into the 19 byte
Transmit FIFO starting with the address field. All the
data must be written to the FIFO in a bytewide
manner. When the data is detected in the transmit
FIFO, the HDLC protocoller will proceed in one of the
following ways:
1) If the transmitter is in idle state, the present byte
2) If the transmitter is in the flag fill state, the
16
Hex
of ones is completely transmitted before sending
the opening flag. The data in the transmit FIFO is
then transmitted.
channel
described
Mechanism to access this channel.
flag presently being transmitted is used as the
opening flag for the packet stored in the transmit
FIFO.
) in Interframe Time Fill state and ends this
will
previously
use
The transmitter is enabled by
A TE transmitting on the D-
the
in
contention
D-channel
circuitry
Priority
3) If
To indicate that the particular byte is the last byte of
the packet, the EOP bit in the HDLC Control Register
2 must be set before the last byte is written into the
transmit FIFO. The EOP bit is cleared automatically
when the data byte is written to the FIFO. After the
transmission of the last byte in the packet, the frame
check sequence (16 bits) is sent followed by a
closing flag. If there is any more data in the transmit
FIFO, it is immediately sent after the closing flag.
That is, the closing flag of a packet is also used as
the opening flag the the next packet.
However,
Recommendations state that after the successful
transmission of a packet, a TE must lower its priority
level within the specified priority class. The user can
meet this requirement by loading the Tx FIFO with no
more than one packet and then waiting for the
DCack bit to go to zero, or for an HDLC interrupt by
the TEOP bit in the HDLC Interrupt Status Register,
before attempting to load a new packet. If there is no
more data to be transmitted, the transmitter assumes
the selected link channel state.
During the transmission of either the data or the
frame check sequence, the Protocol Controller
checks the transmitted information on a bit by bit
basis to insert a ZERO after every sequence of five
consecutive ONEs. This is required to eliminate the
possibility of imitating the opening or closing flag, the
idle code or an abort sequence.
i) Transmit Underrun
A transmit underrun occurs when the last byte
loaded into the transmit FIFO was not ‘flagged’ with
the ‘end of packet’ (EOP) bit and there are no more
bytes in the FIFO. In such a situation, the Protocol
Controller transmits the abort sequence (zero and
seven ones) and moves to the selected link channel
state.
Conversely, in the event that the transmit FIFO is full,
any further writes will overwrite the last byte in the
Transmit FIFO.
ii) Abort Transmission
If it is desired to abort the packet currently being
loaded into the transmit FIFO, the next byte written
to the FIFO should be ‘flagged’ to cause this to
happen. The FA bit of the HDLC Control Register 2
data mode, the protocol functions are disabled
and the data in the transmit FIFO is transmitted
without a framing structure.
the HDLC transmitter
CCITT
I.430
and
is
Data Sheet
ANSI
in transparent
T1.605