MT8930CE Zarlink Semiconductor, MT8930CE Datasheet - Page 20

• Manufacturer Part Number: MT8930CE
• Description: Description = 4 Wire Full-duplex 2B+D (192Kb/s) Data Format Isdn S And T Subscriber Network Interface Circuit With Controllerless Mode ;; Package Type = Pdip ;; No. Of Pins = 28
• Manufacturer: Zarlink Semiconductor

MT8930C
Note 2: These bits will be reset after a write to the TxFIFO
20
B7-B5
B7-B6
B5-B4
B3-B2
BIT
BIT
B4
B3
B2
B1
B0
B1
B0
RxFIFO
TxFIFO
RxByte
EOP
NAME
NAME
Status
Status
Status
RxRst
TxRst
Trans
FA
Idle
NA
Int
(2)
(2)
Keep at ’0’ for normal operation.
A ’1’ will place the HDLC in a transparent mode. This will perform the serial to parallel or
parallel to serial conversion without inserting or deleting the opening and closing flags,
CRC bytes or zero insertion. The source or destination of the data is determined by the
port selection bits in the HDLC Control Register 1.
A transition from ‘0’ to ’1’ will reset the receive FIFO. This causes the receiver to be
disabled until the reception of the next flag. (The status Register will identify the RxFIFO
as being empty). The device resets this bit to ‘0’ immediately after clearing the receive
FIFO.
A transition from ‘0’ to ’1’ will reset the transmit FIFO. This causes the transmitter to
clear all data in the TxFIFO. The device resets this bit to ‘0’ immediately after clearing
the transmit FIFO.
A ’1’ will ’tag’ the next byte written to the transmit FIFO and cause an abort sequence to
be transmitted once it reaches the bottom of the FIFO.
A ’1’ will ’tag’ the next byte written to the transmit FIFO and cause an end of packet
sequence to be transmitted once it reaches the bottom of the FIFO.
These two bits indicate the status of the received byte which is ready to be read from the
19 deep received FIFO. The status is encoded as follows:
These two bits indicate the status of the 19 deep receive FIFO. This status is encoded
as follows:
These two bits indicate the status of the 19 deep transmit FIFO as follows:
If ’1’, an idle channel state has been detected.
If ’1’ an unmasked asynchronous interrupt has been detected.
Table 7. HDLC Control Register 2 (Write Add. 00011
Table 8. HDLC Status Register (Read Add. 00011
B7 -B6
B5 - B4
B3 - B2
0 - 0
0 - 1
1 - 0
1 - 1
0 - 0
0 - 0
1 - 0
1 - 1
0 - 0
0 - 1
1 - 0
1 - 1
- Packet Byte
- First Byte
- Last Byte (Good FCS)
- Last Byte (Bad FCS)
- Rx FIFO Empty
- ≤14 Bytes
- Rx FIFO Overflow
- ≥15 Bytes
- Tx FIFO Full
- ≥5 Bytes
- Tx FIFO Empty
- ≤ Bytes
DESCRIPTION
DESCRIPTION
B
)
B
)
Data Sheet