ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 87

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72344xx ST72345xx
11.1.7
11.1.8
11.1.9
11.1.10
Note:
Hardware watchdog option
If hardware watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the WDGCR is not used. Refer to the Option Byte description.
Using Halt mode with the WDG (WDGHALT option)
The following recommendation applies if Halt mode is used when the watchdog is enabled.
●
Interrupts
None.
Register description
Control register (WDGCR)
Reset value: 0111 1111 (7Fh)
Bit 7 = WDGA Activation bit.
This bit is not used if the hardware watchdog option is enabled by option byte.
Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB).
Window register (WDGWR)
Reset value: 0111 1111 (7Fh)
Bit 7 = Reserved
Bits 6:0 = W[6:0] 7-bit window value
WDGA
Before executing the HALT instruction, refresh the WDG counter, to avoid an
unexpected WDG reset immediately after waking up the microcontroller.
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1,
the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
These bits contain the value of the watchdog counter. It is decremented every 16384
f
becomes cleared).
These bits contain the window value to be compared to the downcounter.
OSC2
7
7
-
cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6
W6
T6
W5
T5
Doc ID 12321 Rev 5
Read/Write
Read/Write
W4
T4
W3
T3
W2
T2
On-chip peripherals
W1
T1
W0
T0
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0