ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 46

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

Supply, reset and clock management
7.4.2
Note:
7.5
7.5.1
Note:
Caution:
46/247
RC control register (RCCRL)
Reset value: 0000 0011 (03h)
Bits 7:2 = Reserved, must be kept cleared.
Bits 1:0 = CR[1:0] RC Oscillator Frequency Adjustment Bits
To tune the oscillator, write a series of different values in the register until the correct
frequency is reached. The fastest method is to use a dichotomy starting with 200h.
Reset sequence manager (RSM)
Introduction
The reset sequence manager includes three reset sources as shown in
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A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to
These sources act on the RESET pin and it is always kept low during the delay phase.
The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic reset sequence consists of 3 phases as shown in
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When the ST7 is unprogrammed or fully erased, the Flash is blank and the reset vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that
recovery has taken place from the Reset state. The shorter or longer clock cycle delay
should be selected by option byte to correspond to the stabilization time of the external
oscillator used in the application (see
The reset vector fetch phase duration is 2 clock cycles.
This 10-bit value must be written immediately after reset to adjust the RC oscillator
frequency in order to obtain the specified accuracy. The application can store the
correct value for each voltage range in EEPROM and write it to this register at startup.
0000h = maximum available frequency
03FFh = lowest available frequency
External RESET source pulse
Internal LVD reset (low voltage detection)
Internal watchdog reset
Active phase depending on the reset source
256 or 4096 CPU clock cycle delay (selected by option byte)
reset vector fetch
7
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Section 12.2.1: Illegal opcode reset on page 196
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Doc ID 12321 Rev 5
Section 15.1 on page
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Read/Write
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for further details.
232).
Figure
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15:
ST72344xx ST72345xx
Figure
CR1
16:
CR0
0