ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 126

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
Note:
Note:
Note:
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Bit 4 = MSTR Master Mode
Bit 3 = CPOL Clock Polarity
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.
Bit 2 = CPHA Clock Phase
The slave must have the same CPOL and CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial clock frequency
These 2 bits have no effect in slave mode.
Table 54.
SPI control/status register (SPICSR)
Reset value: 0000 0000 (00h)
7
SPIF
This bit is set and cleared by software. It is also cleared by hardware when, in master
mode, SS = 0 (see
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are reversed.
This bit is set and cleared by software. This bit determines the idle state of the serial
Clock. The CPOL bit affects both the master and slave modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
This bit is set and cleared by software.
0: The first clock transition is the first data capture edge.
1: The second clock transition is the first capture edge.
These bits are set and cleared by software. Used with the SPR2 bit, they select the
baud rate of the SPI serial clock SCK output by the SPI in master mode.
SPI master mode SCK frequency
WCOL
Serial clock
f
f
f
f
CPU
f
f
CPU
CPU
CPU
Read-only
CPU
CPU
/128
/16
/32
/64
/4
/8
Master mode fault (MODF) on page
OVR
Doc ID 12321 Rev 5
MODF
Reserved
SPR2
1
0
1
0
-
121).
SOD
SPR1
0
1
ST72344xx ST72345xx
Read/Write
SSM
0
SPR0
0
1
0
1
SSI