ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 32

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

Data EEPROM
Note:
32/247
Read operation (E2LAT = 0)
The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR
register is cleared.
On this device, Data EEPROM can also be used to execute machine code. Take care not to
write to the Data EEPROM while executing from it. This would result in an unexpected code
being executed.
Write operation (E2LAT = 1)
To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains
cleared). When a write access to the EEPROM area occurs, the value is latched inside the
32 data latches according to its address.
When E2PGM bit is set by the software, all the previous bytes written in the data latches (up
to 32) are programmed in the EEPROM cells. The effective high address (row) is
determined by the last EEPROM write sequence. To avoid wrong programming, the user
must take care that all the bytes written between two programming sequences have the
same high address: only the five Least Significant Bits of the address can change.
The programming cycle is fully completed when the E2PGM bit is cleared.
Care should be taken during the programming cycle. Writing to the same memory location
will over-program the memory (logical AND between the two write access data result)
because the data latches are only cleared at the end of the programming cycle and by the
falling edge of the E2LAT bit.
It is not possible to read the latched data.
This note is illustrated by the
Figure 8.
Data EEPROM programming flowchart
IN EEPROM AREA
READ MODE
E2PGM = 0
READ BYTES
E2LAT = 0
CLEARED BY HARDWARE
Figure
Doc ID 12321 Rev 5
10.
(with the same 11 MSB of the address)
START PROGRAMMING CYCLE
E2PGM=1 (set by software)
WRITE UP TO 32 BYTES
0
IN EEPROM AREA
WRITE MODE
E2PGM = 0
E2LAT = 1
E2LAT=1
E2PGM
ST72344xx ST72345xx
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