ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 47

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72344xx ST72345xx
7.5.2
7.5.3
Figure 15. reset sequence phases
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated R
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See
more details.
A reset signal originating from an external source must have a duration of at least t
in order to be recognized (see
MCU can enter reset state even in Halt mode.
Figure 16. Reset block diagram
1. See “Illegal opcode reset” on page 198.for more details on illegal opcode reset conditions.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in the electrical
characteristics section.
If the external RESET pulse is shorter than t
the signal on the RESET pin may be stretched. Otherwise the delay will not be applied (see
long ext. Reset in
device RESET pin acts as an output that is pulled low during at least t
External power-on reset
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until V
the minimum level specified for the selected f
page
A proper reset signal for a slow rising V
RC network connected to the RESET pin.
RESET
202).
Figure
V
Active phase
DD
17). Starting from the external RESET pulse recognition, the
R
ON
Doc ID 12321 Rev 5
Figure
Filter
17). This detection is asynchronous and therefore the
256 or 4096 clock cycles
DD
GENERATOR
Internal Reset
RESET
supply can generally be provided by an external
PULSE
w(RSTL)out
OSC
frequency (see
Supply, reset and clock management
(see short ext. Reset in
vector
Fetch
Section 13 on page 199
Operating conditions on
ILLEGAL OPCODE RESET
WATCHDOG RESET
LVD RESET
w(RSTL)out
ON
weak pull-up
Figure
.
INTERNAL
RESET
DD
h(RSTL)in
is over
47/247
17),
for
(1)