ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 82

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
11
11.1
11.1.1
11.1.2
11.1.3
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On-chip peripherals
Window watchdog (WWDG)
Introduction
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interference or by unforeseen logical conditions, which causes the
application program to abandon its normal sequence. The Watchdog circuit generates an
MCU reset on expiry of a programmed time period, unless the program refreshes the
contents of the downcounter before the T6 bit becomes cleared. An MCU reset is also
generated if the 7-bit downcounter value (in the control register) is refreshed before the
downcounter has reached the window register value. This implies that the counter must be
refreshed in a limited window.
Main features
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Functional description
The counter value stored in the WDGCR register (bits T[6:0]), is decremented every 16384
f
in 64 increments.
If the watchdog is activated (the WDGA bit is set) and when the 7-bit downcounter (T[6:0]
bits) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the
reset pin for typically 30 μs. If the software reloads the counter while the counter is greater
than the value stored in the window register, then a reset is generated.
OSC2
Programmable free-running downcounter
Conditional reset
–
–
Hardware/Software Watchdog activation (selectable by option byte)
Optional reset on HALT instruction (configurable by option byte)
cycles (approx.), and the length of the timeout period can be programmed by the user
Reset (if watchdog activated) when the downcounter value becomes less than 40h
Reset (if watchdog activated) if the downcounter is reloaded outside the window
(see
Figure
40)
Doc ID 12321 Rev 5
ST72344xx ST72345xx