ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 168

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
11.7.3
168/247
Figure 71.
General description
In addition to receiving and transmitting data, I2C3S converts it from serial to parallel format
and vice versa. The interrupts are enabled or disabled by software. The I2C3S is connected
to the I
standard I
transmitter/receiver.
In order to fully emulate standard I
peripheral prevents I
register and the RAM buffers using DMA.
Communication flow
A serial data transfer normally begins with a start condition and ends with a stop condition.
Both start and stop conditions are generated by an external master. Refer to
the standard protocol. The I2C3S is not a master and is not capable of generating a
start/stop condition on the SDA line. The I2C3S is capable of recognizing 3 slave addresses
which are user programmable. The three I
enabled/disabled by software.
Since the I2C3S interface always acts as a slave it does not generate a clock. Data and
addresses are transferred as 8-bit bytes, MSB first. The first byte following the start
condition contains the slave address. A 9th clock pulse follows the 8 clock cycles of a byte
transfer, during which the receiver must send an acknowledge bit to the transmitter.
SDA or SDAI
SCL or SCLI
2
C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected both with a
2
C bus and a Fast I
I
2
C3S interface block diagram
CONTROL LOGIC
2
C clock signal stretching and performs data transfer between the shift
I
I
I
2
2
2
C SLAVE ADDRESS 3
C SLAVE ADDRESS 1
C SLAVE ADDRESS 2
COMPARATOR
2
C bus. The interface operates only in Slave mode as
Doc ID 12321 Rev 5
2
C EEPROM devices with highest transfer speed, the
SHIFT REGISTER
2
Slave 3 Interrupt
C slave addresses can be individually
Slave 1 or 2 Interrupt
8-BIT
DMA
RAM
SLAVE 1 BUFFER
SLAVE 2 BUFFER
SLAVE 3 BUFFER
DATA E
256 BYTES
256 BYTES
128 BYTES
256 BYTES
ST72344xx ST72345xx
SHADOW
REGISTER
2
PROM
CPU
Figure 67
for