ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 118

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
Note:
Note:
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Figure 58. Generic SS timing diagram
Figure 59. Hardware/software slave select management
Master mode operation
In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and
phase are configured by software (refer to the description of the SPICSR register).
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
How to operate the SPI in master mode
To operate the SPI in master mode, perform the following steps in order:
1.
2.
3.
Important: if the SPICSR register is not written first, the SPICR register setting (MSTR bit)
may be not taken into account.
The transmit sequence begins when software writes a byte in the SPIDR register.
MOSI/MISO
Master SS
Slave SS
(if CPHA = 0)
Write to the SPICR register:
–
–
Write to the SPICSR register:
–
Write to the SPICR register:
–
Select the clock frequency by configuring the SPR[2:0] bits.
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.
Figure 60
Note that the slave must have the same CPOL and CPHA settings as the master.
Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin
high for the complete byte transmit sequence.
Set the MSTR and SPE bits
Note that the MSTR and SPE bits remain set only if SS is high).
shows the four possible configurations.
SS external pin
Doc ID 12321 Rev 5
SSI bit
Byte 1
SSM bit
1
0
Byte 2
SS internal
ST72344xx ST72345xx
Byte 3