AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 59

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

7734P–AVR–08/10
• Bit 6 - WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled.
If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the cor-
responding interrupt is executed if time-out in the Watchdog Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the
Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF
automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the
Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDIE
must be set after each interrupt. This should however not be done within the interrupt service routine
itself, as this might compromise the safety-function of the Watchdog System Reset mode. If the interrupt
is not executed before the next time-out, a System Reset will be applied.
Table 7-5.
Note:
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or
change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To
clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing
failure, and a safe start-up after the failure.
• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The
different prescaling values and their corresponding time-out periods are shown in
WDTON
0
0
0
0
1
1. For the WDTON Fuse “1” means unprogrammed while “0” means programmed.
(1)
Watchdog Timer Configuration
WDE
0
0
1
1
x
WDIE
0
1
0
1
x
Mode
Stopped
Interrupt Mode
System Reset Mode
Interrupt and System Reset
Mode
System Reset Mode
Action on Time-out
None
Interrupt
Reset
Interrupt, then go to System
Reset Mode
Reset
AT90PWM81
Table 7-6 on page
60.
59