AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 44

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

6.
6.1
6.2
44
Power Management and Sleep Modes
Sleep Modes
Idle Mode
AT90PWM81
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The
AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s
requirements.
Figure 5-1 on page 27
The figure is helpful in selecting an appropriate sleep mode.
their wake up sources.
Table 6-1.
Notes:
To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP
instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which sleep
mode (Idle, ADC Noise Reduction, Power-down or Standby) will be activated by the SLEEP instruction.
See
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then
halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution
from the instruction following SLEEP. The contents of the register file and SRAM are unaltered when the
device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from
the Reset Vector.
When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stop-
ping the CPU but allowing SPI, Analog Comparator, ADC, Timer/Counters, Watchdog, and the interrupt
system to continue operating. This sleep mode basically halt clk
clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the
Timer Overflow interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog
Comparator can be powered down by clearing the ACnEN bit in the Analog Comparator Control and Sta-
Sleep
Mode
Idle
ADC Noise
Reduction
Power-
down
Standby
Table 6-2 on page 47
(1)
1. Only recommended with external crystal or resonator selected as clock source.
2. Only level interrupt.
Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains
presents the different clock systems in the AT90PWM81, and their distribution.
for a summary.
X
X
X
X
X
Oscillators
X
X
X
Table 6-1
CPU
X
X
X
X
(2)
(2)
(2)
and clk
shows the different sleep modes,
X
X
FLASH
Wake-up Sources
, while allowing the other
X
X
X
X
7734P–AVR–08/10
X
X
X
X
X