AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 141

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

7734P–AVR–08/10
The Input Control Registers are used to configure the 2 PSC’s Retrigger/Fault block A & B. The 2 blocks
are identical, so they are configured on the same way.
• Bit 7 – PCAEnx : PSC n Capture Enable Input Part x
Writing this bit to one enables the capture function when external event occurs on input selected as input
for Part x (see PISELnx1:0 bit in the same register).
• Bit 6 – PISELnx0 : PSC n Input Select for Part x
Together with PISELnx1 in PCNFEn register, defines active signal on PSC module A. See
page 138
• Bit 5 –PELEVnx0 : PSC n Edge Level Selector of Input Part x
Together with PELEVnx1 n PCNFEn register, defines active edge & level on PSC part x ; See
16 on page 138
• Bit 4 – PFLTEnx : PSC n Filter Enable on Input Part x
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated,
the input from the retrigger pin is filtered. The filter function requires four successive equal valued sam-
ples of the retrigger pin for changing its output. The Input Capture is therefore delayed by four oscillator
cycles when the noise canceler is enabled.
• Bit 3:0 – PRFMnx3:0: PSC n Fault Mode
These four bits define the mode of operation of the Fault or Retrigger functions.
(see PSC Functional Specification for more explanations)
Table 12-21.
PRFMnx3:0
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
and
Table 12-19 on page 139
and
Level Sensitivity and Fault Mode Operation
Description
No action, PSC Input is ignored
PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait
PSC Input Mode 2: Stop signal, Execute Opposite Pulse and Wait
PSC Input Mode 3: Stop signal, Execute Opposite Pulse while Fault active
PSC Input Mode 4: Deactivate outputs without changing timing.
PSC Input Mode 5: Stop signal and Insert Dead-Time
PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait.
PSC Input Mode 7: Halt PSC and Wait for Software Action
PSC Input Mode 8: Edge Retrigger PSC
PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC
Table 12-17 on page 138
AT90PWM81
Table 12-18 on
Table 12-
141