AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 19

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

4.3.2
4.3.3
4.3.4
7734P–AVR–08/10
The EEPROM Address Registers – EEARH and EEARL
The EEPROM Data Register – EEDR
The EEPROM Control Register – EECR
• Bits 15..9 – Reserved Bits
These bits are reserved bits in the AT90PWM81 and will always read as zero.
• Bits 8..0 – EEAR8..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512 bytes
EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511. The initial value of
EEAR is undefined. A proper value must be written before the EEPROM may be accessed.
• Bits 7..0 – EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in
the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data
read out from the EEPROM at the address given by EEAR.
• Bits 7 – NVMBSY: Non-volatile memory busy
The NVMBSY bit is a status bit that indicates that the NVM memory (FLASH, EEPROM, Lock-bits) is
busy programming. Once a program operation is started, the bit will be set and it remains set until the pro-
gram operation is completed.
Bits 6 – EEPAGE: EEPROM page access (multiple bytes access mode)
Writing EEPAGE to one enables the multiple bytes access mode. That means that several bytes can be
programmed simultaneously into the EEPROM. When the EEPAGE bit has been written to one, the EEP-
AGE bit remains set until an EEPROM program operation is completed. Alternatively the bit is cleared
when the temporary EEPROM buffer is flushed in software (see EEPMn bits description). Any write to
EEPAGE while EEPE is one will be ignored. See Section “Program multiple bytes in one Atomic opera-
tion”, page 21 for details on how to load data into the temporary EEPROM page and the usage of the
EEPAGE bit.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
15
–
EEAR7
7
R
R/W
0
X
7
NVMBSY
R/W
X
7
EEDR7
R/W
0
14
–
EEAR6
6
R
R/W
0
X
6
EEPAGE
R/W
X
6
EEDR6
R/W
0
13
–
EEAR5
5
R
R/W
0
X
5
EEPM1
R/W
X
5
EEDR5
R/W
0
12
–
EEAR4
4
R
R/W
0
X
EEDR4
0
4
EEPM0
R/W
X
4
R/W
11
–
EEAR3
3
R
R/W
0
X
3
EERIE
R/W
0
3
EEDR3
R/W
0
10
–
EEAR2
2
R
R/W
0
X
2
EEMWE
R/W
0
2
EEDR2
R/W
0
1
EEDR1
R/W
0
1
EEWE
R/W
X
9
–
EEAR1
1
R
R/W
0
X
AT90PWM81
0
EEDR0
R/W
0
0
EERE
R/W
0
8
EEAR8
EEAR0
0
R/W
R/W
X
X
EEARH
EEARL
EEDR
EECR
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