AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 118

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.8.4
12.8.4.1
12.8.4.2
118
AT90PWM81
PSC Input Configuration
Filter Enable
Signal Polarity
Figure 12-20. Burst Generation
The PSC Input Configuration is done by programming bits in configuration registers.
If the “Filter Enable” bit is set, a digital filter of 4 cycles is inserted before evaluation of the signal. The
disable of this function is mainly needed for prescaled PSC clock sources, where the noise cancellation
gives too high latency.
Important: If the digital filter is active, the level sensitivity is true also with a disturbed PSC clock to deac-
tivate the outputs (emergency protection of external component). Likewise when used as fault input, PSCn
Input A or Input B have to go through PSC to act on PSCOUTn0/1/2/3 output. This way needs that
CLK
can deactivate directly the PSC output. Notice that in this case, input is still taken into account as usually
by Input Module System as soon as CLK
Figure 12-21. PSC Input Flittering
One can select the active edge (edge modes) or the active level (level modes) See PELEVnx bit descrip-
tion in Section “PSC n Input A Control Register – PFRCnA”, page 14012.25.10.
PSCOUTn0
PSCOUTn1
PSCn Input A
(high level)
PSCn Input A
(low level)
PSC
is running. So thanks to PSC Asynchronous Output Control bit (PAOCnA/B), PSCnIN0/1 input
PSC Input
Module X
CLK
PSC
OFF
Digital
Filter
4 x CLK
PSC
PSC
is running.
BURST
Ouput
Stage
PSCn Input A or B
PSCOUTnX
PIN
7734P–AVR–08/10