AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 207

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

7734P–AVR–08/10
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at
the following rising edge of the ADC clock cycle. See
page 208
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on
(ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.
The actual sample-and-hold takes place 3.5 ADC clock cycles after the start of a normal conversion and
13.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is
written to the ADC Data Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simul-
taneously. The software may then set ADSC again, and a new conversion will be initiated on the first
rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures a fixed
delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place (four
XXX to be confirmed) two ADC clock cycles after the rising edge on the trigger source signal. Three
additional CPU clock cycles are used for synchronization logic.
In Free Running mode, a new conversion will be started immediately after the conversion completes,
while ADSC remains high. For a summary of conversion times, see
Figure 17-4.
Figure 17-5.
Cycle Number
ADC Clock
ADIF
ADCH
ADCL
ADSC
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
for details on differential conversion timing.
ADC Timing Diagram, First Conversion (Single Conversion Mode)
ADC Timing Diagram, Single Conversion
1
1
2
MUX and REFS
Update
2
3
MUX and REFS
Update
4
12
5
6
13
Sample & Hold
7
14
8
15
9
Sample & Hold
16
10
One Conversion
First Conversion
17
11
“Changing Channel or Reference Selection” on
18
12
13
19
Conversion
Complete
14
20
Table
15
21
16
17-1.
22
Conversion
Complete
Sign and MSB of Result
23
AT90PWM81
LSB of Result
Next Conversion
1
24
2
MUX and REFS
Update
25
3
Sign and MSB of Result
Next
Conversion
1
LSB of Result
2
and REFS
Update
MUX
207
3