AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 262

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

21.8.2
21.8.3
262
AT90PWM81
Data Polling Flash
Data Polling EEPROM
When reading data from the AT90PWM81, data is clocked on the falling edge of SCK. See
for timing details.
To program and verify the AT90PWM81 in the serial programming mode, the following sequence is rec-
ommended (See four byte instruction formats in
When a page is being programmed into the Flash, reading an address location within the page being pro-
grammed will give the value 0xFF. At the time the device is ready for a new page, the programmed value
will read correctly. This is used to determine when the next page can be written. Note that the entire page
is written simultaneously and any address within the page can be used for polling. Data polling of the
Flash will not work for the value 0xFF, so when programming this value, the user will have to wait for at
least t
programming of addresses that are meant to contain 0xFF, can be skipped. See
value.
When a new byte has been written and is being programmed into EEPROM, reading the address location
being programmed will give the value 0xFF. At the time the device is ready for a new byte, the pro-
1.
2.
3.
4.
5.
6.
7.
8.
WD_FLASH
Power-up sequence:
Apply power between V
the programmer can not guarantee that SCK is held low during power-up. In this case, RESET
must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set
to “0”.
Wait for at least 20 ms and enable serial programming by sending the Programming Enable
serial instruction to pin MOSI.
The serial programming instructions will not work if the communication is out of synchroniza-
tion. When in sync. the second byte (0x53), will echo back when issuing the third byte of the
Programming Enable instruction. Whether the echo is correct or not, all four bytes of the
instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and
issue a new Programming Enable command.
The Flash is programmed one page at a time. The memory page is loaded one byte at a time by
supplying the 6 LSB of the address and data together with the Load Program Memory Page
instruction. To ensure correct loading of the page, the data low byte must be loaded before data
high byte is applied for a given address. The Program Memory Page is stored by loading the
Write Program Memory Page instruction with the 8 MSB of the address. If polling is not used,
the user must wait at least t
the serial programming interface before the Flash write operation completes can result in incor-
rect programming.
The EEPROM array is programmed one byte at a time by supplying the address and data
together with the appropriate Write instruction. An EEPROM memory location is first automat-
ically erased before new data is written. If polling is not used, the user must wait at least
t
the data file(s) need to be programmed.
Any memory location can be verified by using the Read instruction which returns the content at
the selected address at serial output MISO.
At the end of the programming session, RESET can be set high to commence normal operation.
Power-off sequence (if needed):
Set RESET to “1”.
Turn V
WD_EEPROM
CC
before programming the next page. As a chip-erased device contains 0xFF in all locations,
power off.
before issuing the next byte. (See
CC
WD_FLASH
and GND while RESET and SCK are set to “0”. In some systems,
before issuing the next page. (See
Table
Table
21-15):
21-14.) In a chip erased device, no 0xFFs in
Table
Table 21-14
21-14.) Accessing
7734P–AVR–08/10
for t
Figure 21-8
WD_FLASH