AT90PWM1 Atmel Corporation, AT90PWM1 Datasheet - Page 33

• Manufacturer Part Number: AT90PWM1
• Manufacturer: Atmel Corporation

Specifications of AT90PWM1

• Flash (kbytes): 8 Kbytes
• Pin Count: 24
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 19
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 105
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 1
• Pwm Channels: 7
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

7.6.2
4378C–AVR–09/08
PLL Control and Status Register – PLLCSR
Table 7-8.
1.
2.
3.
Figure 7-3.
• Bit 7..3 – Res: Reserved Bits
These bits are reserved bits in the AT90PWM1 and always read as zero.
• Bit 2 – PLLF: PLL Factor
The PLLF bit is used to select the division factor of the PLL.
If PLLF is set, the PLL output is 64Mhz.
If PLLF is clear, the PLL output is 32Mhz.
• Bit 1 – PLLE: PLL Enable
Bit
$29 ($29)
Read/Write
Initial Value
CKSEL
Ext Clk
0001
3..0
This value do not provide a proper restart ; do not use PD in this clock scheme
This value do not provide a proper restart ; do not use PD in this clock scheme
This value do not provide a proper restart ; do not use PD in this clock scheme
XTAL1
XTAL2
SUT1..0
Start-up Times when the PLL is selected as system clock
PCK Clocking System AT90PWM2/3
00
01
10
11
RC OSCILLATOR
OSCCAL
8 MHz
R
7
–
0
OSCILLATORS
Start-up Time from Power-down
R
6
–
0
CKSEL3..0
and Power-save
R
5
–
0
6 CK
6 CK
6 CK
DIVIDE
BY 8
(1)
(2)
(3)
R
4
–
0
PLLE
PLL
64x
R
3
–
0
Reserved
Detector
Lock
PLLF
DIVIDE
DIVIDE
R/W
PLLF
BY 2
BY 4
2
0
Additional Delay from Reset
PLLE
R/W
0/1
1
14CK + 64 ms
14CK + 4 ms
(V
AT90PWM1
CC
14CK
= 5.0V)
PLOCK
CLK
PLOCK
CK
R
0
0
PLL
SOURCE
PLLCSR
33