AT90PWM1 Atmel Corporation, AT90PWM1 Datasheet - Page 128
AT90PWM1
Manufacturer Part Number
AT90PWM1
Description
Manufacturer
Atmel Corporation
Specifications of AT90PWM1
Flash (kbytes)
8 Kbytes
Pin Count
24
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
19
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Spi
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 105
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
12
Input Capture Channels
1
Pwm Channels
7
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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Company
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Manufacturer
Quantity
Price
Part Number:
AT90PWM1-16SU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT90PWM161-16MN
Manufacturer:
ATMEL/爱特梅尔
Quantity:
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Part Number:
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Manufacturer:
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Quantity:
20 000
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16.5
16.5.1
128
Functional Description
AT90PWM1
Waveform Cycles
Table 37. Internal Outputs
Note:
The waveform generated by PSC can be described as a sequence of two waveforms.
The first waveform is relative to PSCOUTn0 output and part A of PSC. The part of this waveform
is sub-cycle A in the following figure.
The second waveform is relative to PSCOUTn1 output and part B of PSC. The part of this wave-
form is sub-cycle B in the following figure.
The complete waveform is ended with the end of sub-cycle B. It means at the end of waveform
B.
Figure 16-4. Cycle Presentation in 1, 2 & 4 Ramp Mode
4 Ramp Mode
2 Ramp Mode
1 Ramp Mode
SYnOut
PICRn
[11:0]
IRQPSCn
PSCnASY
StopOut
Name
1. See
2.
Ramp A0
See “Analog Synchronization” on page 152.
Figure 16-38 on page 152
Synchronization Output
PSC n Input Capture Register
Counter value at retriggering event
PSC Interrupt Request : three souces, overflow, fault, and input
capture
Stop Output (for synchronized mode)
Sub-Cycle A
ADC Synchronization (+ Amplifier Syncho. )
Ramp A
Description
Ramp A1
PSC Cycle
Ramp B0
Sub-Cycle B
Ramp B
(1)
Ramp B1
UPDATE
(2)
Signal
Register
12 bits
Signal
Signal
Type
Width
4378C–AVR–09/08
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