AT90PWM1 Atmel Corporation, AT90PWM1 Datasheet - Page 195

• Manufacturer Part Number: AT90PWM1
• Manufacturer: Atmel Corporation

Specifications of AT90PWM1

• Flash (kbytes): 8 Kbytes
• Pin Count: 24
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 19
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 105
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 1
• Pwm Channels: 7
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

19.8.2
4378C–AVR–09/08
ADC Control and Status Register A – ADCSRA
• Bit 3, 2, 1, 0 – MUX3, MUX2, MUX1, MUX0: ADC Channel Selection Bits
These 4 bits determine which analog inputs are connected to the ADC input. The different set-
ting are shown in
Table 63. ADC Input Channel Selection
If these bits are changed during a conversion, the change will not take effect until this conversion
is complete (it means while the ADIF bit in ADCSRA register is set).
Bit
Read/Write
Initial Value
• Bit 7 – ADEN: ADC Enable Bit
Set this bit to enable the ADC.
Clear this bit to disable the ADC.
Clearing this bit while a conversion is running will take effect at the end of the conversion.
• Bit 6– ADSC: ADC Start Conversion Bit
Set this bit to start a conversion in single conversion mode or to start the first conversion in free
running mode.
Cleared by hardware when the conversion is complete. Writing this bit to zero has no effect.
The first conversion performs the initialization of the ADC.
In order to start a conversion on an amplified channel with the AT90PWM1, use the ADCS bit in
ADCSRA register.
MUX3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MUX2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ADEN
R/W
7
0
Table
63.
ADSC
R/W
6
0
MUX1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ADATE
R/W
5
0
ADIF
R
MUX0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4
0
ADIE
R/W
3
0
Description
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
Reserved
Reserved
Reserved
AMP0
Reserved
Reserved
Bandgap
GND
ADPS2
R/W
2
0
ADPS1
R/W
1
0
AT90PWM1
ADPS0
R/W
0
0
ADCSRA
195