PSB 21150 F V1.4 Infineon Technologies, PSB 21150 F V1.4 Datasheet - Page 9

• Manufacturer Part Number: PSB 21150 F V1.4
• Description: IC MODULAR ISDN NT INTELL TQFP64
• Manufacturer: Infineon Technologies

Specifications of PSB 21150 F V1.4

• Function: PC Adapter Circuit
• Interface: HDLC, ISDN, SCI
• Number Of Circuits: 1
• Voltage - Supply: 3.3V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFQFP
• Includes: Activation and Deactivation, D-Channel Access Control, Monitor Channel Handler
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PSB21150FV1.4XT; PSB21150FV14NP; PSB21150FV14XP; SP000007575; SP000007577

List of Figures
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Data Sheet
Logic Symbol of the IPAC-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ISDN PC Adapter Card for S Interface . . . . . . . . . . . . . . . . . . . . . . . . 20
ISDN PC Adapter Card for U or S Interface. . . . . . . . . . . . . . . . . . . . . 21
ISDN Voice/Data Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ISDN Stand-Alone Terminal with POTS Interface . . . . . . . . . . . . . . . . 23
Pin Configuration of the IPAC-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Functional Block Diagram of the IPAC-X . . . . . . . . . . . . . . . . . . . . . . . 33
Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Direct/Indirect Register Address Mode . . . . . . . . . . . . . . . . . . . . . . . . 40
Interrupt Status and Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Timer Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Timer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Timer 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
ACL Indication of Activated Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
ACL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Wiring Configurations in User Premises . . . . . . . . . . . . . . . . . . . . . . . 49
S/T -Interface Line Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Frame Structure at Reference Points S and T (ITU I.430). . . . . . . . . . 51
Multiframe Synchronization using the M-Bit. . . . . . . . . . . . . . . . . . . . . 54
Sampling Time in LT-S / NT Mode (M-Bit input) . . . . . . . . . . . . . . . . . 55
Frame Relationship in LT-S / NT Mode (M-Bit input) . . . . . . . . . . . . . . 55
Frame Relationship in TE / LT-T Mode (M-Bit output) . . . . . . . . . . . . . 56
Data Delay Between IOM-2 and S/T Interface Transparent Mode
(TE mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Data Delay Between IOM-2 and S/T Interface With S/G Bit Evaluation
(TE mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Data Delay Between IOM-2 and S/T Interface With 8 IOM Channels
(LT-S/NT mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Data Delay Between IOM-2 and S/T Interface With 3 IOM Channels
a Maximum Receive Delay(LT-S/NT mode only). . . . . . . . . . . . . . . . . 59
Equivalent Internal Circuit of the Transmitter Stage . . . . . . . . . . . . . . 60
Equivalent Internal Circuit of the Receiver Stage . . . . . . . . . . . . . . . . 61
Connection of Line Transformers and Power Supply to the IPAC-X . . 62
External Circuitry for Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
External Circuitry for Symmetrical Receivers. . . . . . . . . . . . . . . . . . . . 64
External Circuitry for Symmetrical Receivers. . . . . . . . . . . . . . . . . . . . 65
Disabling of S/T Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
External Loop at the S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Clock System of the IPAC-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Phase Relationships of IPAC-X Clock Signals . . . . . . . . . . . . . . . . . . 71
9
PSB/PSF 21150
2003-01-30
IPAC-X
Page