PSB 21150 F V1.4 Infineon Technologies, PSB 21150 F V1.4 Datasheet - Page 71

• Manufacturer Part Number: PSB 21150 F V1.4
• Description: IC MODULAR ISDN NT INTELL TQFP64
• Manufacturer: Infineon Technologies

Specifications of PSB 21150 F V1.4

• Function: PC Adapter Circuit
• Interface: HDLC, ISDN, SCI
• Number Of Circuits: 1
• Voltage - Supply: 3.3V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFQFP
• Includes: Activation and Deactivation, D-Channel Access Control, Monitor Channel Handler
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PSB21150FV1.4XT; PSB21150FV14NP; PSB21150FV14XP; SP000007575; SP000007577

3.4.1
The receive PLL performs phase tracking between the F/L transition of the receive signal
and the recovered clock. Phase adjustment is done by adding or subtracting 0.5 or 1
XTAL period to or from a 1.536-MHz clock cycle. The 1.536-MHz clock is than used to
generate any other clock synchronized to the line.
During (re)synchronization an internal reset condition may effect the 1.536-MHz clock to
have high or low times as short as 130 ns. After the S/T interface frame has achieved
the synchronized state (after three consecutive valid pairs of code violations) the FSC
output in TE mode is set to a specific phase relationship, thus causing once an irregular
FSC timing.
The phase relationships of the clocks are shown in
Figure 38
3.4.2
The timing extraction jitter of the IPAC-X conforms to ITU-T Recommendation I.430
(– 7% to + 7% of the S-interface bit period).
Data Sheet
FSC
7.68 MHz
1536 kHz *
768 kHz
Description of the Receive PLL (DPLL)
Jitter
Phase Relationships of IPAC-X Clock Signals
F-bit
* Synchronous to receive S/T. Duty Ratio 1:1 Normally
71
Figure
Description of Functional Blocks
38.
PSB/PSF 21150
2003-01-30
ITD09664
IPAC-X