PSB 21150 F V1.4 Infineon Technologies, PSB 21150 F V1.4 Datasheet - Page 80

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PSB 21150 F V1.4

Manufacturer Part Number
PSB 21150 F V1.4
Description
IC MODULAR ISDN NT INTELL TQFP64
Manufacturer
Infineon Technologies
Datasheet

Specifications of PSB 21150 F V1.4

Function
PC Adapter Circuit
Interface
HDLC, ISDN, SCI
Number Of Circuits
1
Voltage - Supply
3.3V
Current - Supply
30mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-LFQFP
Includes
Activation and Deactivation, D-Channel Access Control, Monitor Channel Handler
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Other names
PSB21150FV1.4XT
PSB21150FV14NP
PSB21150FV14XP
SP000007575
SP000007577
Indication
Deactivation Request
Reset
Test Mode
Acknowledge
Slip Detected
Resynchronization
during level detect
Deactivation Request
from F6
Power up
Activation request
Activation request loop ARL
Illegal Code Violation
Activation indication
loop
Activation indication
with priority class 8
Activation indication
with priority class 10
Deactivation
confirmation
Data Sheet
Abbr. Code Remark
DR
RES
TMA
SLD
RSY
DR6
PU
AR
CVR
AIL
AI8
AI10
DC
0111 IOM-2 interface clocking is provided.
0000 Deactivation request via S/T-interface if left
0001 Reset acknowledge.
0010 Acknowledge for both SSP and SCP.
0011
0100 Signal received, receiver not synchronous.
0101 Deactivation Request from state F6.
1000 Info 2 received.
1010 Internal or external loop A closed.
1011 Illegal code violation received. This function
1110 Internal or external loop A activated.
1100 Info 4 received,
1101 Info 4 received,
1111 Clocks are disabled if CFS bit of register
from F7/F8.
has to be enabled by setting the EN_ICV bit of
register TR_CONF0.
D-channel priority is 8 or 9.
D-channel priority is 10 or 11.
MODE1 is set to ’1’, quiescent state.
80
Description of Functional Blocks
PSB/PSF 21150
2003-01-30
IPAC-X

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