PSB 21150 F V1.4 Infineon Technologies, PSB 21150 F V1.4 Datasheet - Page 145

• Manufacturer Part Number: PSB 21150 F V1.4
• Description: IC MODULAR ISDN NT INTELL TQFP64
• Manufacturer: Infineon Technologies

Specifications of PSB 21150 F V1.4

• Function: PC Adapter Circuit
• Interface: HDLC, ISDN, SCI
• Number Of Circuits: 1
• Voltage - Supply: 3.3V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFQFP
• Includes: Activation and Deactivation, D-Channel Access Control, Monitor Channel Handler
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PSB21150FV1.4XT; PSB21150FV14NP; PSB21150FV14XP; SP000007575; SP000007577

Transparent Mode 0 (MDS2-0 = ’110’).
Characteristics:
Every received frame is stored in RFIFOx (first byte after opening flag to CRC field).
Additional information can be read from RSTAx.
Transparent Mode 1 (MDS2-0 = ’111’).
Characteristics:
A comparison is performed on the first byte after the opening flag with SAP1, SAP2 and
“group” SAPI (FE
FC
Additional information can be read from RSTAx.
Transparent Mode 2 (MDS2-0 = ’101’).
Characteristics:
A comparison is performed only on the second byte after the opening flag, with TEI1,
TEI2 and group TEI (FF
case of a match the rest of the frame is stored in the RFIFOx. Additional information is
available in RSTAx.
Extended Transparent Mode (MDS2-0 = ’100’).
Characteristics:
In extended transparent mode fully transparent data transmission/reception without
HDLC framing is performed i.e. without FLAG generation/recognition, CRC generation/
check, bitstuffing mechanism. This allows user specific protocol variations.
Also refer to
3.9.2
3.9.2.1
The cyclic receive FIFO buffers with a length of 64-byte for D-channel and 128 byte for
each of the two B-channels have variable FIFO block sizes (thresholds) of
• 4, 8, 16 or 32 bytes for D-channel and
• 8, 16, 32 or 64 bytes for B-channels
which can be selected by setting the corresponding RFBS bits in the EXMx registers.
The variable block size allows an optimized HDLC processing concerning frame length,
I/O throughput and interrupt load.
The transfer protocol between HDLC FIFO and microcontroller is block oriented with the
microcontroller as master. The control of the data transfer between the CPU and the
IPAC-X is handled via interrupts (IPAC-X ® Host) and commands (Host ® IPAC-X).
Data Sheet
H
) for B-channel. In the case of a match, all the following bytes are stored in RFIFOx.
Data Reception
Structure and Control of the Receive FIFO
Chapter
H
/FC
No address recognition
SAPI recognition (D-channel)
High byte address recognition (B-channel)
TEI recognition (D-channel)
Low byte address recognistion (B-channel)
Fully transparent
3.9.5.
H
) for D-channel, and with RAH1, RAH2 and group address (FE
H
) for D-channel, and with RAL1 and RAL2 for B-channel. In
145
Description of Functional Blocks
PSB/PSF 21150
2003-01-30
IPAC-X
H
/