ICS1893Y-10LF IDT, Integrated Device Technology Inc, ICS1893Y-10LF Datasheet - Page 94

• Manufacturer Part Number: ICS1893Y-10LF
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893Y-10LF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: 1893Y-10LF; 800-1935-5; ICS1893Y-10LF

7.12.4 100Base-TX Receive Signal Lost (bit 17.10)
7.12.5 100Base PLL Lock Error (bit 17.9)
ICS1893Y-10 Rev F 1/20/04
If Auto-Negotiation is enabled, these bits continually latch the highest state that the Auto-Negotiation State
Machine achieves. That is, they are updated only if the binary value of the next state is greater than the
binary value of the present state as outlined in
Note:
Table 7-19. Auto-Negotiation State Machine (Progress Monitor)
The 100Base-TX Receive Signal Lost bit indicates to an STA whether the ICS1893Y-10 has lost its
100Base-TX Receive Signal. If this bit is set to a logic:
•
•
This bit is a latching high bit. (For more information on latching high and latching low bits, see
7.1.4.1, “Latching High Bits”
Note:
The Phase-Locked Loop (PLL) Lock Error bit indicates to an STA whether the ICS1893Y-10 has ever
experienced a PLL Lock Error. A PLL Lock Error occurs when the PLL fails to lock onto the incoming
100Base data stream. If this bit is set to a logic:
•
•
This bit is a latching high bit. (For more information on latching high and latching low bits, see
7.1.4.1, “Latching High Bits”
Note:
Auto-Negotiation State Machine
Idle
Parallel Detected
Parallel Detection Failure
Ability Matched
Acknowledge Match Failure
Acknowledge Matched
Consistency Match Failure
Consistency Matched
Auto-Negotiation Completed
Successfully
Zero, it indicates the Receive Signal has remained valid since either the last read or reset of this register.
One, it indicates the Receive Signal was lost since either the last read or reset of this register.
Zero, it indicates that a PLL Lock Error has not occurred since either the last read or reset of this register.
One, it indicates that a PLL Lock Error has occurred since either the last read or reset of this register.
ICS1893Y-10 Data Sheet - Release
An MDIO read of these bits provides a history of the greatest progress achieved by the
auto-negotiation process. In addition, the MDIO read latches the present state of the
Auto-Negotiation State Machine for a subsequent read.
This bit has no definition in 10Base-T mode.
This bit has no definition in 10Base-T mode.
Copyright © 2004, Integrated Circuit Systems, Inc.
and
and
Section 7.1.4.2, “Latching Low
Section 7.1.4.2, “Latching Low
Complete Bit
Negotiation
(Bit 17.4)
Auto-
All rights reserved.
0
0
0
0
0
0
0
0
1
Table
94
Auto-Negotiation Progress Monitor
7-19.
Monitor Bit 2
Negotiation
(Bit 17.13)
Auto-
0
0
0
0
1
1
1
1
0
Bits”.)
Bits”.)
Monitor Bit 1
Chapter 7 Management Register Set
Negotiation
(Bit 17.12)
Auto-
0
0
1
1
0
0
1
1
0
Monitor Bit 0
Negotiation
(Bit 17.11)
Auto-
0
1
0
1
0
1
0
1
0
January, 2004
Section
Section