ICS1893Y-10LF IDT, Integrated Device Technology Inc, ICS1893Y-10LF Datasheet - Page 59

• Manufacturer Part Number: ICS1893Y-10LF
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893Y-10LF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: 1893Y-10LF; 800-1935-5; ICS1893Y-10LF

6.6.2.1 Management Frame Preamble
6.6.2.2 Management Frame Start
6.6.2.3 Management Frame Operation Code
6.6.2.4 Management Frame PHY Address
6.6.2.5 Management Frame Register Address
6.6.2.6 Management Frame Operational Code
ICS1893Y-10 Rev F 1/20/04
The ICS1893Y-10 continually monitors its serial management interface for either valid data or a
Management Frame (MF) Preamble, based upon the setting of the MF Preamble Suppression bit, 1.6.
When the MF Preamble Suppression is disabled, an ICS1893Y-10 waits for a MF Preamble which indicates
the start of an STA transaction. A Management Frame Preamble is a pattern of 32 contiguous logic one bits
on the MDIO pin, along with 32 corresponding clock cycles on the MDC pin.
The ICS1893Y-10 supports the Management Frame (MF) Preamble Suppression capability on its
Management Interface, thereby providing a method to shorten the Management Frame and provide an STA
with faster access to the Management Registers.
The ability to process Management Frames that do not have a preamble is provided by the Management
Frame Preamble Suppression bit, (bit 1.6 in the ICS1893Y-10’s Status Register). This is an ISO/IEC
defined status bit that is intended to provide an indication of whether or not a PHY supports the MF
Preamble Suppression feature. In order to maintain backward compatibility with the ICS1890, which did not
support MF Preamble Suppression, the ICS1893Y-10 MF Preamble Suppression bit is a Command
Override Write bit which defaults to a logic zero. An STA can enable MF Preamble Suppression by writing
a logic one to bit 1.6 subsequent to a write of logic one to the Command Override bit, 16.15. For an
explanation of the Command Override Write bits, see
A valid Management Frame includes a start-of-frame delimiter, SFD, immediately following the preamble.
The SFD bit pattern is 01b and is synchronous with two clock cycles on the MDC pin.
A valid Management Frame includes an operation code (OP) immediately following the start-of-frame
delimiter. There are two valid operation codes: one for reading from a management register, 10b, and one
for writing to a management register, 01b. The ICS1893Y-10 does not respond to the codes 00b and 11b,
which the ISO/IEC specification defines as invalid.
The two-wire, Serial Management Interface is specified to allow busing (that is, the sharing of the two wires
among multiple PHYs). The Management Frame includes a 5-bit PHY Address field, PHYAD, allowing for
32 unique addresses. An STA uniquely identifies each of the PHYs that share a single serial management
interface by using this 5-bit PHY Address field, PHYAD.
Upon receiving a valid STA transaction, during a power-on or hardware reset an ICS1893Y-10 compares
the PHYAD field included within the management frame with the value of its PHYAD bits stored in register
16. (For information on the PHYAD bits, see
match its stored address bits.
A Management Frame includes a 5-bit register address field, REGAD. This field identifies which of the 32
Management Registers are involved in a transaction between an STA and a PHY.
A management frame includes a 2-bit operational code field, OP. If the operation code is a:
•
•
Read, the REGAD field identifies the register used as the source of data returned to the STA by the
ICS1893Y-10.
Write, the REGAD identifies the destination register that is to receive the data sent by the STA to the
ICS1893Y-10.
ICS1893Y-10 - Release
Copyright © 2004, Integrated Circuit Systems, Inc.
Table
All rights reserved.
59
7-16.) An ICS1893Y-10 responds to all transactions that
Section 7.1.2, “Management Register Bit
Chapter 6 Functional Blocks
January, 2004
Access”.