ICS1893Y-10LF IDT, Integrated Device Technology Inc, ICS1893Y-10LF Datasheet - Page 71

• Manufacturer Part Number: ICS1893Y-10LF
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893Y-10LF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: 1893Y-10LF; 800-1935-5; ICS1893Y-10LF

7.3.6 IEEE Reserved Bits (bits 1.10:7)
7.3.7 MF Preamble Suppression (bit 1.6)
7.3.8 Auto-Negotiation Complete (bit 1.5)
ICS1893Y-10 Rev F 1/20/04
The IEEE reserves these bits for future use. When an STA:
•
•
Both the ISO/IEC standard and the ICS1893Y-10 reserve the use of some Management Register bits. ICS
uses some reserved bits to invoke ICS1893Y-10 test functions. To ensure proper operation of the
ICS1893Y-10, an STA must maintain the default value of these bits. Therefore, ICS recommends that an
STA write the default value to all reserved bits during all Management Register write operations.
Reserved bits 1.10:7 are Command Override Write (CW) bits. When bit 16.15, the Command Register
Override bit, is logic:
•
•
Status Register bit 1.6 is the Management Frame (MF) Preamble Suppression bit. The ICS1893Y-10 sets
bit 1.6 to inform the STA of its ability to receive frames that do not have a preamble. When this bit is logic:
•
•
Although the ICS1893Y-10 supports Management Frame Preamble Suppression, its default value for bit
1.6 is logic zero. This default value ensures that bit 1.6 is backward compatible with the ICS1890, which
does not have this capability. As the means of enabling this feature, the ICS1893Y-10 implements bit 1.6 as
a Command Override Write bit, instead of as a Read-Only bit as in the ICS1890. An STA uses the bit 1.6 to
enable MF Preamble Suppression in the ICS1893Y-10. [See the description of bit 16.15, the Command
Override Write Enable bit, in
An STA reads bit 1.5 to determine the state of the ICS1893Y-10 auto-negotiation process. The
ICS1893Y-10 sets the value of this bit using two criteria. When its Auto-Negotiation sublayer is:
•
•
Bit 1.5 is a latching high (LH) bit. (For more information on latching high and latching low bits, see
7.1.4.1, “Latching High Bits”
Note:
Reads a reserved bit, the ICS1893Y-10 returns a logic zero.
Writes a reserved bit, the STA must use the default value specified in this data sheet.
Zero, the ICS1893Y-10 prevents all STA writes to CW bits.
One, an STA can modify the value of these bits.
Zero, the ICS1893Y-10 is indicating it cannot accept frames with a suppressed preamble.
One, the ICS1893Y-10 is indicating it can accept frames that do not have a preamble.
Disabled, the ICS1893Y-10 sets bit 1.5 to logic zero.
Enabled, the ICS1893Y-10 sets bit 1.5 to a value based on the state of the Auto-Negotiation State
Machine. In this case, it sets bit 1.5 to logic one only upon completion of the auto-negotiation process.
This setting indicates to the STA that a link is arbitrated and the contents of Management Registers 4, 5,
and 6 are valid. For details on the auto-negotiation process, see
Auto-Negotiation”.
ICS1893Y-10 - Release
An Auto-Negotiation Restart does not clear an LH bit. However, performing two consecutive reads
of this register provides the present state of the bit.
and
Section 7.11, “Register 16: Extended Control
Copyright © 2004, Integrated Circuit Systems, Inc.
Section 7.1.4.2, “Latching Low
All rights reserved.
71
Bits”.)
Section 6.2, “Functional Block:
Chapter 7 Management Register Set
Register”.]
January, 2004
Section