ICS1893Y-10LF IDT, Integrated Device Technology Inc, ICS1893Y-10LF Datasheet - Page 66

• Manufacturer Part Number: ICS1893Y-10LF
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893Y-10LF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: 1893Y-10LF; 800-1935-5; ICS1893Y-10LF

7.2.2 Loopback Enable (bit 0.14)
7.2.3 Data Rate Select (bit 0.13)
7.2.4 Auto-Negotiation Enable (bit 0.12)
ICS1893Y-10 Rev F 1/20/04
This bit controls the Loopback mode for the ICS1893Y-10. Setting this bit to logic:
•
•
This bit provides a means of controlling the ICS1893Y-10 data rate. Its operation depends on the state of
several other functions, including the HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12).
When the ICS1893Y-10 is configured for:
•
•
This bit provides a means of controlling the ICS1893Y-10 Auto-Negotiation sublayer. Its operation depends
on the HW/SW input pin.
When the ICS1893Y-10 is configured for:
•
•
Zero disables the Loopback mode.
One enables the Loopback mode by disabling the Twisted-Pair Transmitter, the Twisted-Pair Receiver,
and the collision detection circuitry. (The STA can override the ICS1893Y-10 from disabling the collision
detection circuitry in Loopback mode by writing logic one to bit 0.7.) When the ICS1893Y-10 is in
Loopback mode, the data presented at the MAC/repeater transmit interface is internally looped back to
the MAC/repeater receive interface. The delay from the assertion of Transmit Data Enable (TXEN) to the
assertion of Receive Data valid (RXDV) is less than 512 bit times.
Hardware mode (that is, the HW/SW pin is logic zero), the ICS1893Y-10 isolates this bit 0.13 and uses
the 10/100SEL input pin to establish the data rate for the ICS1893Y-10. In this Hardware mode:
Software mode (that is, the HW/SW pin is logic one), the function of bit 0.13 depends on the
Auto-Negotiation Enable bit 0.12. When the Auto-Negotiation sublayer is:
Hardware mode, (that is, the HW/SW pin is logic zero), the ICS1893Y-10 isolates bit 0.12 and uses the
ANSEL (Auto-Negotiation Select) input pin to determine whether to enable the Auto-Negotiation
sublayer.
Note: In Hardware mode, bit 0.12 is undefined.
Software mode, (that is, the HW/SW pin is logic one), bit 0.12 determines whether to enable the
Auto-Negotiation sublayer. When bit 0.12 is logic:
– Bit 0.13 is undefined.
– The ICS1893Y-10 provides a Data Rate Status bit (in the QuickPoll Detailed Status Register, bit
– Enabled, the ICS1893Y-10 isolates bit 0.13 and relies on the results of the auto-negotiation process
– Disabled, bit 0.13 determines the data rate. In this case, setting bit 0.13 to logic:
– Zero:
– One:
ICS1893Y-10 Data Sheet - Release
17.15), which always shows the setting of an active link.
to establish the data rate.
• Zero selects 10-Mbps ICS1893Y-10 operations.
• One selects 100-Mbps ICS1893Y-10 operations.
• The ICS1893Y-10 disables the Auto-Negotiation sublayer.
• The ICS1893Y-10 bit 0.13 (the Data Rate bit) and bit 0.8 (the Duplex Mode bit) determine the data
• The ICS1893Y-10 enables the Auto-Negotiation sublayer.
• The ICS1893Y-10 isolates bit 0.13 and bit 0.8.
rate and the duplex mode.
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
66
Chapter 7 Management Register Set
January, 2004