ICS1893Y-10LF IDT, Integrated Device Technology Inc, ICS1893Y-10LF Datasheet - Page 107

• Manufacturer Part Number: ICS1893Y-10LF
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893Y-10LF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: 1893Y-10LF; 800-1935-5; ICS1893Y-10LF

ICS1893Y-10 Rev F 1/20/04
Table 8-3. PHY Address and LED Pins
P1CL
P2LI
Name
Pin
ICS1893Y-10 - Release
Number
Pin
59
60
Input or
Input or
Output
Output
Type
Pin
Copyright © 2004, Integrated Circuit Systems, Inc.
PHY (Address Bit) 1 / Collision LED.
For more information on this pin, see
As an input pin:
As an output pin:
PHY (Address Bit) 2 / Link Integrity LED.
For more information on this pin, see
As an input pin:
As an output pin:
Caution:
Caution:
•
•
•
•
•
•
•
This multi-function configuration pin is:
– An input pin during either a power-on reset or a hardware reset. In
– An output pin following reset. In this case, this pin provides collision
This pin establishes the address for the ICS1893Y-10. When the signal
on this pin is logic:
– Low, that address bit is set to logic zero.
– High, that address bit is set to logic one.
When the signal on this pin is:
– De-asserted, this state indicates the ICS1893Y-10 does not detect
– Asserted, this state indicates the ICS1893Y-10 detects collisions.
The ICS1893Y-10 asserts its Collision LED for a period of
approximately 70 msec when it detects a collision.
This multi-function configuration pin is:
– An input pin during either a power-on reset or a hardware reset. In
– An output pin following reset. In this case, this pin provides link status
This pins establishes the address for the ICS1893Y-10. When the
signal on this pin is logic:
– Low, that address bit is set to logic zero.
– High, that address bit is set to logic one.
When the signal on this pin is:
– De-asserted, this state indicates the ICS1893Y-10 does not have a
– Asserted, this state indicates the ICS1893Y-10 has a valid link.
this case, this pin configures the ICS1893Y-10 when it is in either
hardware mode or software mode.
status for the ICS1893Y-10.
any collisions.
this case, this pin configures the address of the ICS1893Y-10 when it
is in either hardware mode or software mode.
for the ICS1893Y-10.
link.
This pin must not float. (See the notes at
“Multi-Function (Multiplexed) Pins: PHY Address and LED
Pins”.)
This pin must not float. (See the notes at
“Multi-Function (Multiplexed) Pins: PHY Address and LED
Pins”.)
All rights reserved.
107
Chapter 8 Pin Diagram, Listings, and Descriptions
Pin Description
Section 5.5, “Twisted-Pair
Section 5.8, “Status
Section 8.3.2,
Section 8.3.2,
Interface”.
January, 2004
Interface”.