MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 705

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

This register may be read by the user to determine which interrupt requests are currently in
progress (i.e., the interrupt handler started execution) for each CPM interrupt source. More
than one bit in the CISR may be a one if higher priority CPM interrupts are allowed to inter-
rupt lower priority level interrupts within the same CPM interrupt level. For example, the
TIMER2 interrupt routine could interrupt the handling of the TIMER3 routine, using a special
nesting technique described earlier. During this time, the user would see both the TIMER3
and the TIMER2 bits simultaneously set in the CISR.
7.15.6 Interrupt Handler Examples
The following examples illustrate proper interrupt handling of CPM interrupts. Nesting of
interrupts within the CPM interrupt level is not shown in the following examples.
7.15.6.1 EXAMPLE 1—PC6 INTERRUPT HANDLER. In this example, the CPIC hardware
clears the PC6 bit in the CIPR during the interrupt acknowledge cycle. This is an example
of a handler for an interrupt source without multiple events.
7.15.6.2 EXAMPLE 2—SCC1 INTERRUPT HANDLER. In this example, the CIPR bit
SCC1 remains set as long as one or more unmasked event bits remain in the SCCE1 reg-
ister. This is an example of a handler for an interrupt source with multiple events. Note that
the bit in CIPR does not need to be cleared by the handler, but the bit in CISR does need to
be cleared.
MOTOROLA
1. Vector to interrupt handler.
2. Handle event associated with a change in the state of the port C6 pin.
3. Clear the PC6 bit in the CISR.
4. Execute the RTE instruction.
1. Vector to interrupt handler.
2. Immediately read the SCC1 event register (SCCE1) into a temporary location.
The SCC CISR bit positions are NOT affected by the relative pri-
ority between SCCs (as determined by the SCxP and SPS bits
in the CICR).
If the error vector is taken, no bit in the CISR is set. All undefined
bits in the CISR return zeros when read.
The user can control the extent to which CPM interrupts may in-
terrupt other CPM interrupts by selectively clearing the CISR. A
new interrupt will be processed if it has a higher priority than the
higher priority interrupt having its CISR bit set. Thus, if an inter-
rupt routine lowers the 3-bit mask in the CPU32+ core to the
CPM level minus one and also clears its CISR bit at the begin-
ning of the interrupt routine, a lower priority interrupt can inter-
rupt the higher one, as long as the lower priority interrupt is of
higher priority than any other CISR bits that are currently set.
Freescale Semiconductor, Inc.
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MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTES
CPM Interrupt Controller (CPIC)
7-381