MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 320

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

System Integration Module (SIM60)
Bit 4—Reserved
BCYC1–BCYC0—Burst Length Cycle in Clocks
FCM0–FCM3—Function Code Mask
AM27–AM11—Address Mask
6-76
These bits determine the number of wait states inserted in an MC68040 burst cycle. This
attribute is for the second, third, and fourth access of the burst cycle. Program TCYC3–
TCYC0 for the first access.
This field can be used to mask certain function code bits, allowing more than one address
space type to be assigned to a chip select. Any set bit causes the corresponding function
code pin to be used as part of the address comparison. Any cleared bit masks the corre-
sponding function code bit. If both supervisor data and program accesses are desired,
while ignoring CPU space accesses, then the NCS bit in the GMR should be set.
The address mask field, bits 27–11 of each OR, provides for masking any of the corre-
sponding bits in the associated BR. By masking the address bits independently, external
devices of different address range sizes can be used. Any cleared bit masks the corre-
sponding address bit. Any set bit causes the corresponding address bit to be used in the
comparison with the address pins. Address mask bits can be set or cleared in any order
in the field, allowing a resource to reside in more than one area of the address map. This
field can be read or written at any time.
00 = The burst cycles are 1 clock in length (x,1,1,1).
01 = The burst cycles are 2 clocks in length (x,2,2,2).
10 = The burst cycles are 3 clocks in length (x,3,3,3).
11 = The burst cycles are 4 clocks in length (x,4,4,4).
When the DRAM controller supports MC68EC040 cycles,
PGME must be cleared by the user, or erratic behavior may oc-
cur.
Clear the FCM bits to ignore function codes as part of the ad-
dress comparison.
Regardless of the setting in this register, an external encoding of
X111 of the function code pins will be taken as a CPU space ac-
cess.
When address lines A31–A28 are multiplexed with the WE lines,
the A31–A28 lines are still used in the comparison by an internal
QUICC master. See the base address bit description in 6.13.3
Base Register (BR).
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTES
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MOTOROLA