MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 617

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
Serial Management Controllers (SMCs)
Synchronization can be achieved in two ways. When the transmitter is connected to a TDM
channel, it can be synchronized to a time slot. Once the frame sync is received, the trans-
mitter waits for the first bit of its time slot to occur before transmission begins. Data will only
be transmitted during the time slots defined by the TSA. Secondly, when working with its
own set of pins (nonmultiplexed mode), the transmitter will start transmission when the
SMSYNx line is asserted (falling edge).
When a BD’s data has been completely written to the transmit FIFO, the L-bit is checked. If
the L-bit is set, the SMC writes the message status bits into the BD and clears the R-bit. It
will then start transmitting idles. When the end of the current BD has been reached and the
L-bit is not set (multibuffer mode), only the R-bit is cleared. In both cases, an interrupt is
issued according to the I-bit in the BD. By appropriately setting the I-bit in each BD, inter-
rupts can be generated after the transmission of each buffer, a specific buffer, or each block.
The SMC will then proceed to the next BD in the table.
If no additional buffers have been presented to the SMC for transmission and the L-bit was
cleared, an underrun is detected, and the SMC begins transmitting idles.
If the CM bit is set in the Tx BD, the R-bit will not be cleared, allowing the associated data
buffer to be retransmitted automatically when the CP next accesses this data buffer. For
instance, if a single Tx BD is initialized with the CM bit set and the W-bit set, the data buffer
will be continuously transmitted until the user clears the R-bit of the BD.
7.11.10.5 SMC TRANSPARENT RECEPTION PROCESSING. When the CPU32+ core
enables the SMC receiver in transparent mode, it will wait for synchronization before receiv-
ing data. Once synchronization is achieved, the receiver will transfer the incoming data into
memory according to the first Rx BD in the ring.
Synchronization can be achieved in two ways. When the receiver is connected to a TDM
channel, it can be synchronized to a time slot. Once the frame sync is received, the receiver
waits for the first bit of its time slot to occur before reception begins. Data will only be
received during the time slots defined by the TSA. Secondly, when working with its own set
of pins (nonmultiplexed mode), the receiver will start reception when the SMSYNx line is
asserted (falling edge).
When the data buffer has been filled, the SMC clears the E-bit in the BD and generates an
interrupt if the I-bit in the BD is set. If the incoming data exceeds the length of the data buffer,
the SMC will fetch the next BD in the table and, if it is empty, will continue to transfer data
to this BD’s associated data buffer.
If the CM bit is set in the Rx BD, the E-bit will not be cleared, allowing the associated data
buffer to be overwritten automatically when the CP next accesses this data buffer.
7.11.10.6 USING THE SMSYNx PIN FOR SYNCHRONIZATION. The SMSYNx pin offers
a method to synchronize the SMC channel externally. This method differs somewhat from
the synchronization options available in the SCCs and should be studied carefully. See Fig-
ure 7-78 for an example.
MOTOROLA
MC68360 USER’S MANUAL
7-293
For More Information On This Product,
Go to: www.freescale.com