MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 698

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
CPM Interrupt Controller (CPIC)
The CPIC prioritizes all interrupt sources based upon their assigned priority level. The high-
est priority interrupt request is presented to the CPU32+ core for servicing. After the vector
number corresponding to this interrupt is passed to the CPU32+ core during an interrupt
acknowledge cycle, that interrupt request is cleared. If there are remaining interrupt
requests, they are then prioritized, and another interrupt request may be presented to the
CPU32+ core.
The 3-bit mask in the CPU32+ status register ensures that a subsequent interrupt request
at a higher interrupt priority level will suspend handling of a lower priority interrupt. The mask
indicates the current processor priority, and interrupts are inhibited for all priority levels less
than or equal to the current processor priority.
The CISR and the mask register in the CPU32+ core can be used together to allow a higher
priority interrupt within the same interrupt level to be presented to the CPU32+ core before
the servicing of a lower priority interrupt is completed. Each bit in the CISR corresponds to
a CPM interrupt source. During an interrupt acknowledge cycle for a CPM interrupt, the in-
service bit in the CISR is set by the CPIC for that interrupt source. The setting of the bit pre-
vents any subsequent CPM interrupt requests at this priority level or lower (within the CPIC
interrupt table), until the servicing of the current interrupt has completed and the in-service
bit is cleared by the user. (Pending interrupts for these sources are still set in the CPIC dur-
ing this time).
Thus, in the interrupt service routine for the CPM interrupts, the user can lower the core’s
mask to the next lower level (the level being serviced minus 1) to allow higher priority inter-
rupts within this level to generate an interrupt request. This capability provides nesting of
interrupt requests for CPM interrupt level sources in a similar manner as the CPU32+ core’s
interrupt mask provides nesting of interrupt requests for the seven interrupt priority levels.
7.15.3 Masking Interrupt Sources in the CPM
By programming the CPM interrupt mask register (CIMR), the user may mask the CPM inter-
rupts to prevent an interrupt request to the CPU32+ core. Each bit in the CIMR corresponds
to one of the CPM interrupt sources. To enable an interrupt, write a one to the corresponding
CIMR bit.
When a masked CPM interrupt source has a pending interrupt request, the corresponding
bit in the CIPR is still set, even though the interrupt is not generated to the CPU32+ core. By
masking all interrupt sources in the CIMR, the user may implement a polling interrupt ser-
vicing scheme for the CPM interrupts.
When a CPM interrupt source has multiple interrupting events, the user can individually
mask these events by programming a mask register within that block. Table 7-22 indicates
the interrupt sources that have multiple interrupting events. Figure 7-100 shows an example
of how the masking occurs, using an SCC as an example.
7-374
MC68360 USER’S MANUAL
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