MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 441

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

TPL—Tx Preamble Length
TPP—Tx Preamble Pattern
Tend—Transmitter Frame Ending
TDCR—Transmit Divide Clock Rate
MOTOROLA
The TPL bits determine the length of the preamble configured by the TPP bits.
The TPP bits determine what, if any, bit pattern should precede the start of each transmit
frame. The preamble pattern will be sent prior to the first flag/sync of the frame. TPP is
ignored if the SCC is programmed to UART mode. The length of the preamble is pro-
grammed in TPL. The preamble pattern is typically transmitted to a receiving station that
uses a DPLL for clock recovery. The receiving DPLL uses the regular pattern of the pre-
amble to help it lock onto the received signal in a short, predictable time period.
This bit is intended particularly for the NMSI transmitter encoding of the DPLL. Tend de-
termines whether the TXD line should idle in a high state or in an encoded ones state
(which may be either high or low). It may, however, be used with other encodings besides
NMSI.
The TDCR bits determine the divider rate of the transmitter. If the DPLL is not used, the
1 value should be chosen, except in asynchronous UART mode where 8 , 16 , or 32
must be chosen. The user should program TDCR to equal RDCR in most applications.
If the DPLL is used in the application, the selection of TDCR depends on the encoding.
NRZI usualy requires 1 ; whereas, FM0/FM1, Manchester, and Differential Manchester
allow 8 , 16 , or 32 . The 8 option allows highest speed; whereas, the 32 option pro-
vides the greatest resolution. TDCR is usually equal to RDCR to allow the same clock fre-
quency source to control both the transmitter and receiver.
000 = No preamble (default)
001 = 8 bits (1 byte)
010 = 16 bits (2 bytes)
011 = 32 bits (4 bytes)
100 = 48 bits (6 bytes) (Select this setting for Ethernet operation.)
101 = 64 bits (8 bytes)
110 = 128 bits (16 bytes)
111 = Reserved
00 = All zeros
01 = Repeating 10’s (Select this setting for Ethernet operation.)
10 = Repeating 01’s
11 = All ones (Select this setting for LocalTalk operation.)
0 = Default operation. The TXD line is encoded only when data is transmitted (includ-
1 = The TXD line is always encoded (even when idles are transmitted).
00 = 1 clock mode (Only NRZ or NRZI encodings are allowed.)
01 = 8 clock mode
10 = 16 clock mode (normally chosen for UART and AppleTalk)
11 = 32 clock mode
ing the preamble and opening and closing flags/syncs). When no data is available
to transmit, the line is driven high.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Serial Communication Controllers (SCCs)
7-117