MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 103

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MC68MH360EM25L

Manufacturer Part Number
MC68MH360EM25L
Description
IC MPU QUICC ETHER 25MHZ 240FQFP
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MC68MH360EM25L

Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-

Available stocks

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Manufacturer
Quantity
Price
Part Number:
MC68MH360EM25L
Manufacturer:
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Quantity:
1
State 0—The write cycle starts in S0. During S0, the QUICC places a valid address on A31–
A0 and valid function codes on FC3–FC0. The function codes select the address space for
the cycle. The QUICC drives R/W low for a write cycle. SIZ1 and SIZ0 become valid, indi-
cating the number of bytes to be transferred.
State 1—One-half clock later during S1, the QUICC asserts AS, indicating a valid address
on the address bus. During this state, any or all of the byte write enables (WE0, WE1, WE2,
and WE3) are asserted simultaneously with AS.
State 2—During S2, the QUICC places the data to be written onto D31–D0 and samples
DSACKx at the end of S2.
MOTOROLA
FC3–FC0
DSACK0
DSACK1
A31–A2
CLKO1
D31–D0
NOTE: WE3–WE0 is not shown.
R/W
SIZ1
SIZ0
AS
DS
A0
A1
S0
LONG WORD
S2
READ
Figure 4-20. Read-Write-Read Cycles—32-Bit Port
S4
Freescale Semiconductor, Inc.
For More Information On This Product,
S0
MC68360 USER’S MANUAL
Go to: www.freescale.com
S2
WRITE
S4
S0
S2
WRITE
S4
S0
S2
READ WITH WAIT STATES
Sw
Bus Operation
Sw
S4
4-27

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