MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 184

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
CPU32+
tiated while an instruction is executing. Several bus error stack format organizations are uti-
lized to provide additional information regarding the nature of the fault.
First, any register altered by a faulted-instruction EA calculation is restored to its initial value.
Then a special status word (SSW) is placed on the stack. The SSW contains specific infor-
mation about the aborted access—size, type of access (read or write), bus cycle type, and
function code. Finally, fault address, bus error exception vector number, PC value, and a
copy of the SR are saved.
If a bus error occurs during exception processing for a bus error, an address error, a reset,
or while the processor is loading stack information during RTE execution, the processor
halts. This simplifies isolation of catastrophic system failure by preventing processor inter-
action with stacks and memory. Only assertion of RESET can restart a halted processor.
5.5.2.3 ADDRESS ERROR. Address error exceptions occur when the processor attempts
to access an instruction, word operand, or long-word operand at an odd address. The effect
is much the same as an internally generated bus error. The exception processing sequence
is the same as that for bus error, except that the vector number refers to the address error
exception vector.
Address error exception processing begins when the processor attempts to use information
from the aborted bus cycle. If the aborted cycle is a data space access, exception process-
ing begins when the processor attempts to use the data, except in the case of a released
operand write. Released write exceptions are delayed until the next instruction boundary or
attempted operand access.
An address exception on a branch to an odd address is delayed until the PC is changed. No
exception occurs if the branch is not taken. In this case, the fault address and return PC
value placed in the exception stack frame are the odd address, and the current instruction
PC points to the instruction that caused the exception.
If an address error occurs during exception processing for a bus error, another address
error, or a reset, the processor halts.
5.5.2.4 INSTRUCTION TRAPS. Traps are exceptions caused by instructions. They arise
from either processor recognition of abnormal conditions during instruction execution or
from use of specific trapping instructions. Traps are generally used to handle abnormal con-
ditions that arise in control routines.
The TRAP instruction, which always forces an exception, is useful for implementing system
calls for user programs. The TRAPcc, TRAPV, CHK, and CHK2 instructions force excep-
tions when a program detects a run-time error. The DIVS and DIVU instructions force an
exception if a division operation is attempted with a divisor of zero.
Exception processing for traps follows the regular sequence. If tracing is enabled when an
instruction that causes a trap begins execution, a trace exception will be generated by the
instruction, but the trap handler routine will not be traced. (The trap exception will be pro-
cessed first, then the trace exception.)
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MC68360 USER’S MANUAL
MOTOROLA
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