MC68MH360EM25L Freescale Semiconductor, MC68MH360EM25L Datasheet - Page 7

• Manufacturer Part Number: MC68MH360EM25L
• Description: IC MPU QUICC ETHER 25MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

3.1
3.2
3.3
3.3.1
3.3.2
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
4.1.9.1
4.1.9.2
4.1.9.3
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.4.1
4.4.4.2
4.4.4.3
4.5
4.5.1
4.5.2
4.5.3
4.5.4
Paragraph
Number
MOTOROLA
Dual-Port RAM Memory Map .................................................................. 3-2
CPM Sub-Module Base Addresses......................................................... 3-3
Internal Registers Memory Map .............................................................. 3-4
SIM Registers Memory Map.................................................................... 3-4
CPM Registers Memory Map .................................................................. 3-6
Bus Transfer Signals ............................................................................... 4-2
Bus Control Signals................................................................................. 4-3
Function Codes (FC3–FC0) .................................................................... 4-3
Address Bus (A31–A0)............................................................................ 4-4
Address Strobe (AS) ............................................................................... 4-4
Data Bus (D31-D0).................................................................................. 4-4
Data Strobe (DS)..................................................................................... 4-4
Output Enable (OE)................................................................................. 4-4
Byte Write Enable (WE0, WE1, WE2, WE3) ........................................... 4-4
Bus Cycle Termination Signals ............................................................... 4-5
Data transfer and size acknowledge (DSACK1 and DSACK0). .............. 4-5
Bus Error (BERR).................................................................................... 4-5
Autovector (AVEC). ................................................................................. 4-6
Data Transfer Mechanism ....................................................................... 4-6
Dynamic Bus Sizing ................................................................................ 4-6
Misaligned Operands ............................................................................ 4-11
Effects of Dynamic Bus Sizing and Operand Misalignment .................. 4-19
Bus Operation ....................................................................................... 4-20
Synchronous Operation with DSACKx .................................................. 4-21
Fast Termination Cycles........................................................................ 4-21
Data Transfer Cycles............................................................................. 4-22
Read Cycle............................................................................................ 4-23
Write Cycle ............................................................................................ 4-26
Read-Modify-Write Cycle ...................................................................... 4-28
CPU Space Cycles................................................................................ 4-31
Breakpoint Acknowledge Cycle............................................................. 4-31
LPSTOP Broadcast Cycle ..................................................................... 4-35
Module Base Address Register (MBAR) Access .................................. 4-36
Interrupt Acknowledge Bus Cycles........................................................ 4-36
Interrupt Acknowledge Cycle—Terminated Normally............................ 4-36
Autovector Interrupt Acknowledge Cycle. ............................................. 4-38
Spurious Interrupt Cycle........................................................................ 4-40
Bus Exception Control Cycles ............................................................... 4-41
Bus Errors ............................................................................................. 4-42
Retry Operation ..................................................................................... 4-44
Halt Operation ....................................................................................... 4-46
Double Bus Fault................................................................................... 4-48
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
QUICC Memory Map
Go to: www.freescale.com
Bus Operation
Section 4
Title
Table of Contents
Number
Page
iii