PIC18F65K90T-I/PT Microchip Technology, PIC18F65K90T-I/PT Datasheet - Page 447

• Manufacturer Part Number: PIC18F65K90T-I/PT
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90T-I/PT

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Details

28.6
The user program memory is divided into four blocks
for the PIC18FX5K90 device and PIC18FX6K90
devices, and eight blocks for PIC18FX7K90 devices.
One of these is a boot block of 1 or 2 Kbytes. The
remainder of the memory is divided into blocks on
binary boundaries.
FIGURE 28-6:
 2009-2011 Microchip Technology Inc.
3FFFFFh
Note 1:
01FFFFh
000000h
200000h
Program Verification and
Code Protection
2:
Unimplemented
Unimplemented
Code Memory
Configuration
Sizes of memory areas are not to scale.
Boot block size is determined by the BBSIZ0 bit (CONFIG4L<4>).
Read as ‘ 0 ’
Read as ‘
and ID
Space
CODE-PROTECTED PROGRAM MEMORY FOR THE PIC18F87K90 FAMILY
0
’
BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0
Block 0
Block 1
Block 2
Block 3
Block 4
Block 5
Block 6
Block 7
Block
2 kW
6 kW
8 kW
8 kW
8 kW
8 kW
8 kW
8 kW
8 kW
Boot
PIC18FX7K90
Block 0
Block 1
Block 2
Block 3
Block 4
Block 5
Block 6
Block 7
Block
7 kW
8 kW
8 kW
8 kW
8 kW
8 kW
8 kW
8 kW
Boot
PIC18F87K90 FAMILY
Each of the blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 28-6
48, 64, 96 and 128-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in
Device/Memory Size
Block 0
Block 1
Block 2
Block 3
Block
2 kW
6 kW
8 kW
8 kW
8 kW
Boot
PIC18FX6K90
shows the program memory organization for
Block 0
Block 1
Block 2
Block 3
Block
7 kW
8 kW
8 kW
8 kW
Boot
(2)
Boot Block
Block 0
Block 1
Block 2
Block 3
2 kW
2 kW
4 kW
4 kW
4 kW
PIC18FX5K90
Block 0
Block 1
Block 2
Block 3
Block
3 kW
4 kW
4 kW
4 kW
Boot
DS39957D-page 447
Table
0000h
0800h
1000h
17FFh
1800
3FFF
4000h
5FFFh
6000h
7FFF
8000h
BFFFh
C000h
FFFFh
10000h
13FFFh
14000h
17FFFh
18000h
1BFFFh
1C000h
1FFFFh
Address
28-4.
(1)